SC186 datasheet(15/18 Pages) SEMTECH

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SC186

Under-Voltage Lockout

Under-Voltage Lockout (UVLO) is enabled when the input

voltage drops below the UVLO threshold. This prevents

the device from entering an ambiguous state in which

regulation cannot be maintained. Hysteresis of approxi-

mately 300mV is included to prevent chattering near the

threshold. When the AVIN voltage rises back to the turn-

on threshold and CTL

X is high, the soft-start mode is

resumed.

Power Good

The power good (PGOOD) is an open-drain output. When

the output voltage drops below 10% of nominal voltage,

the PGOOD pin is pulled low after a 20μs delay. During

start-up, PGOOD will be asserted 2ms (typ.) after the

output voltage reaches 90% of the final regulation voltage.

The faults of over voltage, fold-back current limit mode

and thermal shutdown will force PGOOD low after a 20µs

delay. When recovering from a fault, PGOOD will be

asserted 1.8ms (typ.) after Vout reaches 90% of the final

regulation voltage.

Soft-Start

The soft-start mode is activated after AVIN reaches it’s

UVLO voltage threshold and CTL

X is set high to enable the

part. A thermal shutdown event will also activate the soft

start sequence. The soft-start mode controls the slew-rate

of the output voltage during start-up thus limiting in-rush

current on the input supply. During start-up, the reference

voltage for the error amplifier is clamped by the voltage

on the SS pin. The output voltage slew rate during soft-

start is determined by the value of the external capacitor

connected to the SS pin and the internal 5µA charging

current. The device requires a minimum soft-start time

from enable to final regulation in the order of 200µs,

including the 50µs enable delay. As a result the soft start

capacitor, Css, should be higher than 1.5nF. During start

up, the chip operates in forced PWM mode.

100% Duty-Cycle Operation

SC186 is capable of operating at 100% duty-cycle. When

the difference between the input voltage and output

voltage is less than the minimum dropout voltage, the

PMOS switch is completely on, operating in 100% duty-

cycle. The minimum dropout voltage is the output current

Applications Information (continued)

multiplied by the on-resistance of the internal PMOS

switch and the DC-resistance of the inductor when PMOS

switch is on continuously.

Output L-C filter Selection

SC186 has fixed internal loop-gain compensation. It

is optimized for X5R or X7R ceramic output capacitors

and an output L-C filter corner frequency of less

than 34kHz. The output L-C corner frequency can be

determined by Equation 2.

OUT

In general, the inductor is chosen to set the inductor ripple

current to approximately 30% of the maximum output

current. It is recommended to use a typical inductor value

of 1μH to 2.2μH with output ceramic capacitors of 44μF or

higher capacitance. Lower inductance should be consid-

ered in applications where faster transient response is

required. More output capacitance will reduce the output

deviation for a particular load transient. When using low

inductance, the maximum peak inductor current at any

condition (normal operation and start up) can not exceed

5A which is the guaranteed minimum current limit. The

saturation current rating of the inductor needs to be at

least larger than the peak inductor current which is the

maximum output current plus half of inductor ripple

current.

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