TC11IB datasheet(49/108 Pages) INFINEON

49 / 108 page

TC11IB

Data Sheet

V2.3, 2003-11

Note: Accesses to address defined as “Reserved” in Table 3 lead to a bus error.The

exceptions are marked with 1)

Memory Protection System

The TC11IB memory protection system specifies the addressable range and read/write

permissions of memory segments available to the currently executing task. The memory

protection system controls the position and range of addressable segments in memory.

It also controls the kinds of read and write operations allowed within addressable

memory segments. Any illegal memory access is detected by the memory protection

hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the

error. Thus, the memory protection system protects critical system functions against both

software and hardware errors. The memory protection hardware can also generate

signals to the Debug Unit to facilitate tracing illegal memory accesses.

In SAF-T11IB-64D96, TriCore supports two address spaces: The virtual address space

and The physical address space. Both address space are 4GB in size and divided into

16 segments with each segment being 256MB. The upper 4 bits of the 32-bit address are

used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address

is always translated into a physical address before accessing memory. The virtual

address is translated into a physical address using one of two translation mechanisms:

(a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual

address belongs to the upper half of the virtual address space then the virtual address is

directly used as the physical address (direct translation). If the virtual address belongs to

the lower half of the address space, then the virtual address is used directly as the

physical address if the processor is operating in Physical mode (direct translation) or

translated using a Page Table Entry if the processor is operating in Virtual mode (PTE

translation). These are managed by Memory Management Unit (MMU)

Memory protection is enforced using separate mechanisms for the two translation paths.

Protection for direct translation

Memory protection for addresses that undergo direct translation is enforced using the

range based protection that has been used in the previous generation of the TriCore

architecture. The range based protection mechanism provides support for protecting

memory ranges from unauthorized read, write, or instruction fetch accesses. The

TriCore architecture provides up to four protection register sets with the PSW.PRS field

controlling the selection of the protection register set. Because the TC11IB uses a

Harvard-style memory architecture, each Memory Protection Register Set is broken

down into a Data Protection Register Set and a Code Protection Register Set. Each Data

Protection Register Set can specify up to four address ranges to receive particular

protection modes. Each Code Protection Register Set can specify up to two address

ranges to receive particular protection modes.

TC11IB Datasheet(PDF) 49 Page - Infineon Technologies AG