| Electronic Components Datasheet Search |
|
ICS1524 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS1524 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
|
1 / 24 page ![]() Integrated Circuit Systems, Inc. General Description Features ICS1524 ICS1524 Rev C 01/31/2003 Block Diagram Dual Output Phase Controlled SSTL_3/PECL Clock Generator • Wide input frequency range • 8 kHz to 100 MHz • 250 MHz balanced PECL differential outputs • 150 MHz single-ended SSTL_3 clock outputs • Dynamic Phase Adjust (DPA) for DPACLK outputs • Software controlled phase adjustment • 360o Adjustment down to 1/64 clock increments • External or internal loop filter selection • Uses 3.3 VDC Inputs are 5 volt tolerant. •I2C-bus serial interface runs at either low speed (100 kHz) or high speed (400 kHz). • Hardware and Software PLL Lock detection The ICS1524 is a low-cost, very high-performance frequency generator and phase controlled clock synthe- sizer. It is perfectly suited to phase controlled clock synthesis and distribution as well as line-locked and genlocked applications. The ICS1524 offers two channels of clock phase con- trolled outputs; CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL’s input and the DPACLK uses the Dynamic Phase Adjust cir- cuitry to allow control of the clock phase relative to input signal. Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, en- abling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regener- ated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal program- mable feedback divider or an external divider and is programmed by a standard I2C-bus™ serial interface. I 2 C-bus is a trademark of Philips Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Applications • Generic Frequency Synthesis • LCD Monitors and Projectors • Genlocking Multiple Video Systems HSYNC OSC IC 2 DPACLK+/- FUNC DPACLK Loop Filter CLK+/- CLK Pin Configuration 24 Pin 300-mil SOIC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDDD VSSD SDA SCL PDEN EXTFB HSYNC EXTFIL XFILRET VDDA VSSA OSC IREF CLK+ (PECL) C VSSQ VDDQ CLK (SSTL) CLK (SSTL) FUNC (SSTL) LOCK/REF (SSTL) ICADR LK– (PECL) DPACLK+ (PECL) DPACLK– (PECL) DPA 2 |
Similar Part No. - ICS1524 |
|
Similar Description - ICS1524 |
|
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |