CLC410 datasheet(13/16 Pages) TI1

13 / 16 page

OBSOLETE

CLC410

www.ti.com

SNOS854D – AUGUST 2000 – REVISED APRIL 2013

where

•

AVis the non-inverting gain

(3)

Note that with AV = +2 we get the specified Rf = 250Ω, while at higher gains, a lower value gives stable

performance with improved bandwidth.

DC ACCURACY AND NOISE

Since the two inputs for the CLC410 are quite dissimilar, the noise and offset error performance differs somewhat

from that of a standard differential input amplifier. Specifically, the inverting input current noise is much larger

than the non-inverting current noise. Also the two input bias currents are physically unrelated rendering bias

current cancellation through matching of the inverting and non-inverting pin resistors ineffective.

In Equation 4, the output offset is the algebraic sum of the equivalent input voltage and current sources that

influence DC operation. Output noise is determined similarly except that a root-sum-of-squares replaces the

algebraic sum. Rs is the non-inverting pin resistance.

Equation

Output Offset VO=±IBN× RS(1+Rf/Rg)± VIO (1+Rf/Rg)±IBI× Rf

(4)

An important observation is that for fixed Rf, offsets as referred to the input improve as the gain is increased

(divide all terms by 1+Rf/Rg). A similar result is obtained for noise where noise figure improves as a gain

increases.

The input noise plot shown in the CLC400 datasheet applies equally as well to the CLC410.

CAPACITIVE FEEDBACK

Capacitive feedback should not be used with the CLC410 because of the potential for loop instability. See

Application Note OA-7 for active filter realizations with the CLC410.

OFFSET ADJUSTMENT PIN

Pin 1 can be connected to a potentiometer as shown in Figure 19 and used to adjust the input offset of the

CLC410. Full range adjustment of ±5V on pin 1 will yield a ±10mV input offset adjustment range. Pin 1 should

always be bypassed to ground with a ceramic capacitor located close to the package for best settling

performance.

PRINTED CIRCUIT LAYOUT

As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and

good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting

configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting

node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the

feedback resistor should not be used to compensate for this effect.

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CLC410 Datasheet(PDF) 13 Page - Texas Instruments