Vertical and

Horizontal

LCD

Timing

Control

SWAP

FRC

Clock and

Data

Synchronizer

RSDS

Interface

with

Skew

Control

RTC

Data

Processor

Frame Memory

(64 Mb SDRAM)

DE

Filter

SSC

Internal

ROM

LUT

Register

2-wire serial

EEPROM

Interface

FPD-Link

Receiver

RxIN0P/N

RxIN1P/N

RxIN2P/N

RxIN3P/N

RxCLKP/N

RESETN

TEST

Control Options

SSCKO

SSCKI

SSCTR

SCL

SDA

RSF/BR[3:0]P/N

RGB

data

RSKEW[2:0]

PI

RSF/BG[3:0]P/N

RSF/BB[3:0]P/N

RSF/BCKP/N

TP

POL

F/BSTH

CPV

OE

STV

RVC

RGB

data

DE

DCLK

DE_in

DCLK_in

DATA_in

MCLK, RAM interface

Mth frame RGB data

M-1th frame

RGB data

Mth frame

RGB data

DCLK, SYNC, DE

OBSOLETE

FPD87352

www.ti.com

SNOSAG3C – JULY 2004 – REVISED APRIL 2013

Block Diagram

Figure 2. Block Diagram

Function Description

FPD-LINK RECEIVER

The LVDS based FPD-Link Receiver receives input video data and control timing. Four LVDS channels plus

clock provide 24-bit color.

RESETN initializes the chip with the default register values for the LUT values from internal ROM or external

EEPROM.

SSC (SPREAD SPECTRUM CONTROL)

This SSC function provides a means for reducing EMI. This feature uses external SSC signal source that

provides synchronized spread spectrum for RSDS and control signal outputs.

2-WIRE SERIAL EEPROM INTERFACE

The Serial EEPROM Interface controls the FPD87352CXA initialization of LUT register. If the EEPROM is not

present, the LUT value is provided by internal ROM of FPD87352CXA.

CLK & DATA SYNCHRONIZER

This function delays and aligns data to match the internal data process which included RSDS skew control by

RSKEW[2:0]. All the data processes are needed to be aligned each data path through RSDS output and LCD

timing control signal.

Copyright © 2004–2013, Texas Instruments Incorporated

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