LXT972ALC datasheet(13/70 Pages) INTEL

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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A

Datasheet

2.0

Signal Descriptions

Table 2.

LXT972A MII Signal Descriptions

LQFP

Pin#

Symbol

Type1

Signal Description

Data Interface Pins

TXD3

TXD2

TXD1

TXD0

Transmit Data. TXD is a bundle of parallel data signals that are driven by the MAC.

TXD<3:0> shall transition synchronously with respect to the TX_CLK. TXD<0> is the least

significant bit.

TX_EN

Transmit Enable. The MAC asserts this signal when it drives valid data on TXD. This

signal must be synchronized to TX_CLK.

TX_CLK

Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100Mbps operations. 2.5

MHz for 10Mbps operation, 25 MHz for 100Mbps operation.

RXD3

RXD2

RXD1

RXD0

Receive Data. RXD is a bundle of parallel signals that transition synchronously with

respect to the RX_CLK. RXD<0> is the least significant bit.

RX_DV

Receive Data Valid. The LXT972A asserts this signal when it drives valid data on RXD.

This output is synchronous to RX_CLK.

RX_ER

Receive Error. Signals a receive error condition has occurred. This output is synchronous

to RX_CLK.

TX_ER

Transmit Error. Signals a transmit error condition. This signal must be synchronized to

TX_CLK.

RX_CLK

Receive Clock. 25 MHz for 100Mbps operation, 2.5 MHz for 10Mbps operation. Refer to

“Clock Requirements” on page 20 in the Functional Description section.

COL

Collision Detected. The LXT972A asserts this output when a collision is detected. This

output remains High for the duration of the collision. This signal is asynchronous and is

inactive during full-duplex operation.

CRS

Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts this output

when either transmitting or receiving data packets. During full-duplex operation (bit 0.8 = 1),

CRS is asserted during receive. CRS assertion is asynchronous with respect to RX_CLK.

CRS is de-asserted on loss of carrier, synchronous to RX_CLK.

MII Control Interface Pins

MDDIS

Management Disable. When MDDIS is High, the MDIO is disabled from read and write

operations.

When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only

the initial or “default” values of their respective register bits. After the power-up/reset cycle

is complete, bit control reverts to the MDIO serial channel.

MDC

Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is

8 MHz.

MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel for PHY/STA

communication.

MDINT

Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates

status change. Interrupt is cleared by reading Register 19.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.

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