LXT972ALC datasheet(39/70 Pages) INTEL

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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A

Datasheet

3.10.2

State Machine

The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the

TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are

high for five TCK periods.

3.10.3

Instruction Register

After the state machine resets, the IDCODE instruction is always invoked. The decode logic

ensures the correct data flow to the Data registers according to the current instruction. Valid

instructions are listed in Table 12.

3.10.4

Boundary Scan Register (BSR)

Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the

serial shift stage and the parallel output stage. There are four modes of operation as listed in Table

11.

Table 11. BSR Mode of Operation

Mode

Description

Capture

2Shift

Update

System Function

Table 12. Supported JTAG Instructions

Name

Code

Description

Mode

Data Register

EXTEST

0000

External Test

Test

BSR

IDCODE

0001

ID Code Inspection

Normal

ID REG

SAMPLE

0010

Sample Boundary

Normal

BSR

TRIBYP

0011

Force Float

Normal

Bypass

SETBYP

0100

Control Boundary to 1/0

Test

Bypass

BYPASS

1111

Bypass Scan

Normal

Bypass

Table 13. Device ID Register

31:28

27:12

11:8

7:1

Version

Part ID (hex)

Jedec Continuation Characters

JEDEC ID1

Reserved

0001

03CB

1110

111 1110

1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE (1111 1110) which becomes

111 1110

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