AD6649EBZ datasheet(39/40 Pages) AD

39 / 40 page

Data Sheet

AD6649

Rev. C | Page 39 of 40

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD6649,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD6649, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD), and a separate supply should be used

for the digital outputs (DRVDD). The designer can employ

several different decoupling capacitors to cover both high and

low frequencies. These capacitors should be located close to the

point of entry at the PC board level and close to the pins of the

part with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD6649. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD6649 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC

and the PCB, a silkscreen should be overlaid to partition the

continuous plane on the PCB into several uniform sections.

This provides several tie points between the ADC and the PCB

during the reflow process. Using one continuous plane with no

partitions guarantees only one tie point between the ADC and

the PCB. See the evaluation board for a PCB layout example.

For detailed information about packaging and PCB layout of

chip scale packages, refer to the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP).

VCM

The VCM pin should be decoupled to ground with a 0.1 μF

capacitor, as shown in Figure 28. For optimal channel-to-channel

isolation, a 33 Ω resistor should be included between the AD6649

VCM pin and the Channel A analog input network connection

and between the AD6649 VCM pin and the Channel B analog

input network connection.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD6649 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

AD6649EBZ Datasheet(PDF) 39 Page - Analog Devices

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