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ADC0811 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # ADC0811
Description  8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer
PDF  14 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC0811 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics
The following specifications apply for VCC e 475V to 525V VREF ea46V to (VCC a 01V) w2 CLK e 2097 MHz unless
otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C (Continued)
Parameter
Conditions
ADC0811CCJ
ADC0811BCN ADC0811BCV
Units
ADC0811CCN ADC0811CCV
Typical
Tested
Design
Typical
Tested
Design
(Note 6)
Limit
Limit
(Note 6)
Limit
Limit
(Note 7)
(Note 8)
(Note 7)
(Note 8)
DIGITAL AND DC CHARACTERISTICS
VIN(1) Logical ‘‘1’’ Input
VCCe525V
20
20
20
V
Voltage (Min)
VIN(0) Logical ‘‘0’’ Input
VCCe475V
08
08
08
V
Voltage (Max)
IIN(1) Logical ‘‘1’’ Input
VINe50V
0005
25
0005
25
25
m
A
Current (Max)
IIN(0) Logical ‘‘0’’ Input
VINe0V
b
0005
b
25
b
0005
25
b
25
m
A
Current (Max)
VOUT(1) Logical ‘‘1’’
VCCe475V
Output Voltage (Min)
IOUTeb360 mA
24
24
24
V
IOUTeb10 mA
45
45
45
V
VOUT(0) Logical ‘‘0’’
VCCe525V
04
04
04
V
Output Voltage (Max)
IOUTe16 mA
IOUT TRI-STATE Output
VOUTe0V
b
001
b
3
b
001
b
3
b
3
m
A
Current (Max)
VOUTe5V
001
3
001
3
3
m
A
ISOURCE Output Source
VOUTe0V
b
12
b
65
b
14
b
65
b
65
mA
Current (Min)
ISINK Output Sink Current (Min)
VOUTeVCC
18
80
16
80
80
mA
ICC Supply Current (Max)
CSe1 VREF Open
1
25
1
25
25
mA
IREF (Max)
VREFe5V
07
1
07
1
1
mA
AC CHARACTERISTICS
Tested
Design
Parameter
Conditions
Typical
Limit
Limit
Units
(Note 6)
(Note 7)
(Note 8)
w CLK w Clock Frequency
MIN
10
MHz
MAX
21
SCLK Serial Data Clock
MIN
50
KHz
Frequency
MAX
525
TC Conversion Process Time
MIN
Not Including MUX
48
w
cycles
Addressing and
MAX
Analog Input
64
Sampling Times
tACC Access Time Delay From CS
MIN
1
w
cycles
Falling Edge to DO Data Valid
MAX
3
tSETUP Minimum Setup Time of CS Falling
4 w2CLKa
1
2SCLK
sec
Edge to SCLK Rising Edge
tHCS CS Hold Time After the Falling
0
ns
Edge of SCLK
t CS Total CS Low Time
MIN
tset-upa8SCLK
sec
MAX
t CS(min)a48 w2CLK
sec
tHDI Minimum DI Hold Time from
0
ns
SCLK Rising Edge
tHDO Minimum DO Hold Time from SCLK
RLe
k
10
ns
Falling Edge
CLe
pF
3



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