ADC0811 datasheet(9/14 Pages) NSC

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Functional Description

10 DIGITAL INTERFACE

The ADC0811 uses five inputoutput pins to implement the

serial interface Taking chip select (CS) low enables the IO

data lines (DO and DI) and the serial clock input (SCLK) The

result of the last conversion is transmitted by the AD on the

DO line while simultaneously the DI line receives the ad-

dress data that selects the mux channel for the next conver-

sion The mux address is shifted in on the rising edge of

SCLK and the conversion data is shifted out on the falling

edge It takes eight SCLK cycles to complete the serial IO

A second clock (w2) controls the SAR during the conversion

process and must be continuously enabled

11 CONTINUOUS SCLK

With a continuous SCLK input CS must be used to synchro-

nize the serial data exchange (see

Figure 1 ) The ADC0811

recognizes a valid CS one to three w2 clock periods after

the actual falling edge of CS This is implemented to ensure

noise immunity of the CS signal Any spikes on CS less than

one w2 clock period will be ignored CS must remain low

during the complete IO exchange which takes eight SCLK

cycles Although CS is not immediately acknowledged for

the purpose of starting a new conversion the falling edge of

CS immediately enables DO to output the MSB (D7) of the

previous conversion

The first SCLK rising edge will be acknowledged after a set-

up time (tset-up) has elapsed from the falling edge of CS

This and the following seven SCLK rising edges will shift in

the channel address for the analog multiplexer Since there are

12 channels only four address bits are utilized The first four

SCLK cycles clock in the mux address during the next four

SCLK cycles the analog input is selected and sampled During

this mux addresssample cycle data from the last conver-

sion is also clocked out on DO Since D7 was clocked out

on the falling edge of CS only data bits D6 – D0 remain to be

received The following seven falling edges of SCLK shift out

this data on DO

The 8th SCLK falling edge initiates the beginning of the AD’s

actual conversion process which takes between 48 to 64 w2

cycles (TC) During this time CS can go high to TRI-STATE

DO and disable the SCLK input or it can remain low If CS is

held low a new IO exchange will not start until the conver-

sion sequence has been completed however once the con-

version ends serial IO will immediately begin Since there is

an ambiguity in the conversion time (TC) synchronizing the

data exchange is impossible Therefore CS should go high

before the 48th w2 clock has elasped and return low after

the 64th w2 to synchronize serial communication

A conversion or IO operation can be aborted at any time by

strobing CS IfCS is high or low less than one w2 clock it will

be ignored by the AD If the CS is strobed high or low

between 1 to 3 w2 clocks the AD may or may not respond

Therefore CS must be strobed high or low greater than 3 w2

clocks to ensure recognition If a conversion or IO ex-

change is aborted while in process the consequent data

output will be erroneous until a complete conversion se-

quence has been implemented

12 DISCONTINUOUS SCLK

Another way to accomplish synchronous serial communica-

tion is to tie CS low continuously and disable SCLK after its

8th falling edge (see

Figure 2 ) SCLK must remain low for

TLH5587 – 18

FIGURE 1

TLH5587 – 19

FIGURE 2

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