TPS23751PWPR datasheet(21/52 Pages) TI1

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TPS23751, TPS23752

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SLVSB97D – JULY 2012 – REVISED JANUARY 2016

Device Functional Modes (continued)

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input

requirements differ from PSE output requirements to account for voltage drops and operating margin. The

standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.

IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-

568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage

drops have been adjusted for 12.5

Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568,

typically AWG 24 conductors). Table 2 shows key operational limits broken out for the two revisions of the

standard.

Table 2. Comparison of Operational Limits

Power Loop

PSE Static

Static PD Input Voltage

PSE Output

PD Input

Resistance

Output

Standard

Power (min)

Power (max)

Power

≤ 12.95W

Power > 12.95W

(max)

Voltage (min)

IEEE802.3at-2008

Ω

15.4W

44 V

12.95W

37 V – 57 V

N/A

802.3at (Type 1)

802.3at (Type 2)

12.5

Ω

30W

50 V

25.5W

37 V – 57 V

42.5 V – 57 V

The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT),

or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT

systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare

pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges

to accept power from any of the possible PSE configurations. The voltage drops associated with the input

bridges create a difference between the standard limits at the PI and the TPS23751 and TPS23752

specifications.

A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements

include the following:

1. Must interpret type 2 hardware classification,

2. Must present hardware class 4,

3. Must implement DLL negotiation,

4. Must behave like a type 1 PD during inrush and startup,

5. Must not draw more than 13W for 80ms after the PSE applies operating voltage (power-up),

6. Must not draw more than 13W if it has not received a type 2 hardware classification or received permission

through DLL,

7. Must meet various operating and transient templates, and

8. Optionally monitor for the presence or absence of an adapter (assume high power).

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for

changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the

adapter should be individually monitored, typically with an optocoupler.

7.4.1.1 Threshold Voltages

The TPS23751 and TPS23752 have a number of internal comparators with hysteresis for stable switching

between the various states. Figure 23 relates the parameters in the Electrical Characteristics section to the PoE

states. The mode labeled Idle between Classification and Operation implies that the DEN, CLS, and RTN pins

are all high impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2

hardware class state machine.

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