TPS23751PWPR datasheet(33/52 Pages) TI1

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TPS23751, TPS23752

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SLVSB97D – JULY 2012 – REVISED JANUARY 2016

Typical Application (continued)

8.2.2 Detailed Design Procedure

8.2.2.1 Input Bridges and Schottky Diodes

Using Schottky diodes instead of PN junction diodes for the PoE input bridges reduces the power dissipation in

these devices by about 30%. There are, however, some things to consider when using them.

The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100-k

Ω resistor is placed between the

unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse

leakage current than PN diodes, making this a harder requirement to meet. To compensate, use conservative

design for diode operating temperature, select lower-leakage devices where possible, and match leakage and

temperatures by using packaged bridges.

Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting

reasonable expectations for the temperature range over which the detection signature is accurate is the simplest

solution. Increasing RDEN slightly may also help meet the requirement.

Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After

exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate

protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors.

As a general recommendation, use 1 A or 2 A, 100-V rated discrete or bridge diodes for the input rectifiers.

8.2.2.2 Protection, D1

A TVS, D1, across the rectified PoE voltage per Figure 31 must be used. A SMAJ58A, or equivalent, is

recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient

voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional

protection.

8.2.2.3 Capacitor, C1

The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF. Typically

a 0.1

μF, 100 V, 10% ceramic capacitor is used.

8.2.2.4 Detection Resistor, RDEN

The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.75 kΩ and 26.25 kΩ, or

25 k

Ω ±5%. A resistor of 24.9 kΩ ±1% is recommended for RDEN.

8.2.2.5 Classification Resistor, RCLS

Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at standard.

The class power assigned should correspond to the maximum average power drawn by the PD during operation.

Select RCLS according to Table 1. For a high power design, choose class 4 and RCLS = 63.4 Ω.

8.2.2.6 APD Pin Divider Network, RAPD1, RAPD2

The APD pin can be used to disable the TPS23751 and TPS23752 internal hotswap MOSFET, giving the

adapter source priority over the PoE. For an example calculation, see literature number SLVA306.

8.2.2.7 Setting the PWM-VFO Threshold using the SRT pin

The TPS23751 and TPS23752 internally compares modified voltages at the SRT and CTL pins to determine the

operating mode. The designer should consider the light load operating point (considering the value of VCTL)

where synchronous rectifier (M2 in Figure 31) gate drive and switching losses nearly match conduction losses of

the rectifier diode (DOUT in Figure 31). Typically, the designer characterizes circuit efficiency, output load, and

control pin (VCTL) voltage and then select the transition point. Both VFO → PWM (occurs at higher load current

due to natural hysteresis) and PWM

→ VFO (occurs at slightly lower load current) transitions should be

considered when choosing the VSRT setpoint. As an example:

1. Assume that the desired efficiency transition threshold occurs at 18% of full load and VCTL = 2.0 V

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