9

PI6CFGL601B

RevA

01/16/15

PI6CFGL601B

6-Output Low Power PCIE Gen 1-2-3 Clock Generator

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Symbol

Parameters

Condition

Min.

Typ.

Max.

Units

I

IN

Single-ended inputs, V

(exclude XTAL_IN pin)

-5

5

uA

I

INP

Single-ended inputs

V

tors

V

resistors

-200

200

uA

Tind

Ambient Operating

Industrial range

-40

85

°C

F

in

XTAL_IN

25.000

MHz

L

pin

7

nH

C

IN

Logic Inputs

1.5

5

pF

C

INXTAL

Crystal inputs

6

pF

C

OUT

Output pin capacitance

6

pF

T

STAB

From V

stabilization to 1st clock

1.8

ms

f

MODIN

SS Modulation Fre-

Allowable Frequency (Triangular Modulation) 30

31.500 33

kHz

t

F

Fall time of control inputs

5

ns

t

R

Rise time of control inputs

5

ns

V

ILSMB

SMBus Input Low

0.8

V

V

IHSMB

SMBus Input High

2.1

V

DDSMB

V

V

OLSMB

SMBus Output Low

@ I

PULLUP

0.4

V

I

PULLUP

@ V

OL

4

mA

V

DDSMB

3V to 5V +/- 10%

2.7

5.5

V

t

RSMB

SCLK/SDATA Rise

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

t

FSMB

SCLK/SDATA Fall

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

f

MAXSMB

SMBus Operating

Delay from assertion of first output enable reg-

ister to first clock Maximum SMBus operating

frequency

100

kHz

Notes:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Control input must be monotonic from 20% to 80% of input swing.

15-0018