10

PI6CFGL601B

RevA

01/16/15

PI6CFGL601B

6-Output Low Power PCIE Gen 1-2-3 Clock Generator

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Electrical Characteristics–CLK 0.7V Low Power Differential Outputs

T

o

C; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for loading conditions

Symbol

Parameters

Condition

Min. Typ. Max. Units

Trf

Scope averaging on

1

4

V/ns

ΔTrf

Slew rate matching, Scope averaging on

20

%

VHigh

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope averag-

ing on)

660

850

mV

VLow

-150

150

Vmax

Measurement on single ended signal using abso-

lute value. (Scope averaging off)

1150

mV

Vmin

-300

Vswing

Scope averaging off

300

mV

Vcross_abs

Scope averaging off

300

550

mV

Δ-Vcross

Scope averaging off

140

mV

Notes:

1. Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential trace impedance).

2. Measured from differential waveform.

3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.

4. Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where

Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations.

5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and

Clock# falling).

6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is

to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross abs.

Electrical Characteristics–Phase Jitter Parameters

T

o

C; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions

Symbol

Parameters

Condition

Min. Typ.

INDUSTRY

LIMIT

Units

t

jphPCIeG1

Phase Jitter, PCI

PCIe Gen 1

27

86

ps

(p-p)

t

jphPCIeG2

Phase Jitter, PCI

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

0.5

3

ps

(rms)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.1

3.1

ps

(rms)

t

jphPCIeG3

Phase Jitter, PCI

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.5

1

ps

(rms)

Notes:

1. Guaranteed by design and characterization, not 100% tested in production.

2. See http://www.pcisig.com for complete specs.

3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

4. Calculated from Intel-supplied Clock Jitter Tool.

5. Applies to all different outputs.

15-0018