ADC12041 datasheet(21/28 Pages) NSC

21 / 28 page

Features and Operating Modes

(Continued)

Since the bus width of the ADC12041 defaults to 8 bits after

power-up, the first action when 13-bit mode is desired must

be to set the bus width to 13 bits.

WMODE

The WMODE pin is used to determine the active edge of the

write pulse. The state of this pin determines which edge of

the WR signal will cause the ADC to latch in data. This is pro-

cessor dependent. If the processor has valid data on the bus

during the falling edge of the WR signal, the WMODE pin

must be tied to V

D+. This will cause the ADC to latch the data

on the falling edge of the WR signal. If data is valid on the ris-

ing edge of the WR signal, the WMODE pin must be tied to

DGND causing the ADC to latch in the data on the rising

edge of the WR signal.

ANALOG INPUTS

The ADCIN+ and ADCIN− are the fully differential noninvert-

ing (positive) and inverting (negative) inputs into the

analog-to-digital converter (ADC) of the ADC12041.

STANDBY MODE

The ADC12041 has a low power consumption mode (75 µW

@ 5V). This mode is entered when a Standby command is

written in the command field of the Configuration register.

The RDY ouput pin is high when the ADC12041 is in the

Standby mode. Any command other than the Standby com-

mand written to the Configuration register will get the

ADC12041 out of the Standby mode. The RDY pin will im-

mediately switch to a logic “0” when the ADC12041 is out of

the standby mode. The ADC12041 defaults to the Standby

mode following a hardware power-up.

SYNC/ASYNC MODE

The ADC12041 may be programmed to operate in synchro-

nous (SYNC-IN) or asynchronous (SYNC-OUT) mode. To

enter synchronous mode, the SYNC bit in the Configuration

after a hardware power-up. In this mode, the SYNC pin is

programmed as an input and conversions are synchronized

to the rising edges of the signal applied at the SYNC pin. Ac-

quisition time can also be controlled by the SYNC signal

when in synchronous mode. Refer to the sync-in timing dia-

grams. When the SYNC bit is cleared, the ADC is in asyn-

chronous mode and the SYNC pin is programmed as an out-

put. In asynchronous mode, the signal at the SYNC pin

indicates the status of the converter. This pin is high when

the converter is performing a conversion. Refer to the

sync-out timing diagrams.

SELECTABLE ACQUISITION TIME

The ADC12041’s internal sample/hold circuitry samples an

input voltage by connecting the input to an internal sampling

capacitor (approximately 70 pF) through an effective resis-

tance equal to the “On” resistance of the analog switch at the

input to the sample/hold circuit (2500

Ω typical) and the effec-

tive output resistance of the source. For conversion results

to be accurate, the period during which the sampling capaci-

tor is connected to the source (the “acquisition time”) must

be long enough to charge the capacitor to within a small frac-

tion of an LSB of the input voltage. An acquisition time of 750

ns is sufficient when the external source resistance is less

than 1 k

Ω and any active or reactive source circuitry settles

to 12 bits in less than 500 ns. When source resistance or

source settling time increase beyond these limits, the acqui-

sition time must also be increased to preserve precision.

In asynchronous (SYNC-OUT) mode, the acquisition time is

controlled by an internal counter. The minimum acquisition

period is 9 clock cycles, which corresponds to the nominal

value of 750 ns when the clock frequency is 12 MHz. Bits b

and b

1 of the Configuration Register are used to select the

acquisition time from among four possible values (9, 15, 47,

or 79 clock cycles). Since acquisition time in the asynchro-

nous mode is based on counting clock cycles, it is also in-

versely proportional to clock frequency:

Note that the actual acquisition time will be longer than T

ACQ

because acquisition begins either when the multiplexer

channel is changed or when RDY goes low, if the multiplexer

channel is not changed. After a read is performed, RDY goes

high, which starts the T

ACQ counter (see Figure 9).

In synchronous (SYNC-IN) mode, bits b

0 and b1 are ignored,

and the acquisition time depends on the sync signal applied

to the SYNC pin. The acquisition period begins on the falling

edge of RDY , which occurs at the end of the previous con-

version (or at the end of an autozero or autocalibration pro-

cedure. The acquisition period ends when SYNC goes high.

To estimate the acquisition time necessary for accurate con-

versions when the source resistance is greater than 1 k

Ω,

use the following expression:

where R

S is the source resistance, and RS/H is the sample/

hold “On” resistance.

If the settling time of the source is greater than 500 ns, the

acquisition time should be about 300 ns longer than the set-

tling time for a “well-behaved”, smooth settling characteristic.

FULL CALIBRATION CYCLE

A full calibration cycle compensates for the ADC’s linearity

and offset errors. The converter’s DC specifications are

guaranteed only after a full calibration has been performed.

A full calibration cycle is initated by writing a Ful-Cal com-

mand to the ADC12041. During a full calibration, the offset

error is measured eight times, averaged and a correction co-

efficient is created. The offset correction coefficient is stored

in an internal offset correction register.

The overall linearity correction is achieved by correcting the

internal DAC’s capacitor mismatches. Each capacitor is

compared eight times against all remaining smaller value ca-

pacitors. The errors are averaged out and correction coeffi-

cients are created.

Once the converter has been calibrated, an arithmetic logic

unit (ALU) uses the offset and linearity correction coefficients

to reduce the conversion offset and linearity errors to within

guaranteed limits.

AUTO-ZERO CYCLE

During an auto-zero cycle, the offset is measured only once

and a correction coefficient is created and stored in an inter-

nal offset register. An auto-zero cycle is initiated by writing an

Auto-Zero command to the ADC12041.

ADC12041 Datasheet(PDF) 21 Page - National Semiconductor (TI)

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