ADC12048 datasheet(8/30 Pages) NSC

8 / 30 page

Digital Timing Characteristics (Continued)

The following specifications apply to the ADC12048, 13-bit data bus width, V

A+=VD+ = 5V, fCLK = 12 MHz, tf = 3 ns and CL

= 50 pF on data I/O lines

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 10)

(Note 11)

(Limit)

RDDATA

Falling Edge of RD to Valid Data

13-Bit Mode (BW Bit = “1”)

ns (max)

RDHOLD

Read Hold Time

ns (max)

RDRDY

Rising Edge of RD to Rising Edge of

RDY

ns (max)

WRRDY

Active Edge of WR to Rising Edge of

RDY

WMODE = “1”

ns (max)

STNDBY

Active Edge of WR to Falling Edge of

STDBY

WMODE = “0”. Writing the

Standby Command into the

Configuration Register

200

230

ns (max)

STDONE

Active Edge of WR to Rising Edge of

STDBY

WMODE = “0”. Writing the

RESET Command into the

Configuration Register

ns (max)

STDRDY

Active Edge of WR to Falling Edge of

RDY

WMODE = “0”. Writing the

RESET Command into the

Configuration Register

1.4

2.5

ms (max)

SYNC

Minimum SYNC Pulse Width

ns (min)

Notes on Specifications

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-

tions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA+orVD+)), the current at that pin should be limited to

30 mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.

Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by TJmax, (maximum junction temperature), θJA (package junc-

tion to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax =(TJmax −TA)/θJA or

the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C, and the typical thermal resistance (θJA) of the ADC12048

in the V package, when board mounted, is 55˚C/W, and in the VF package, when board mounted, is 67.8˚C/W.

Note 5: Human body model, 100 pF discharged through 1.5 k

Ω resistor.

Note 6: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above

VA+ or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D

conversion can occur if these diodes are forward biased by more than 50 mV. As an example, if VA+ is 4.50 VDC, full-scale input voltage must be ≤ 4.55 VDC to ensure

accurate conversions.

Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V

+ pin to assure conversion/

comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.

Note 8: Accuracy is guaranteed when operating at fCLK = 12 MHz.

Note 9: With the test condition for VREF (VREF+−VREF−) given as +4.096V, the 12-bit LSB is 1.000 mV.

Note 10: Typicals are at TA = 25˚C and represent most likely parametric norm.

Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.

DS012387-4

ADC12048 Datasheet(PDF) 8 Page - National Semiconductor (TI)

ADC12048 Datasheet(HTML) 8 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL