ADC12451 datasheet(12/18 Pages) NSC

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10 Pin Descriptions

DVCC (24)

The digital and analog positive power supply

AVCC (4)

pins The digital and analog power supply

voltage range of the ADC12451 is a45V to

55V To guarantee accuracy it is required

that the AVCC and DVCC be connected to-

gether to the same power supply with sepa-

rate bypass capacitors (10 mF tantalum in

parallel with a 01 mF ceramic) at each VCC

(5)

The analog negative supply voltage pin Vb

has a range of b45V to b55V and needs

bypass capacitors of 10 mF tantalum in paral-

lel with a 01 mF ceramic

DGND (12)

The digital and analog ground pins AGND

AGND (3)

and DGND must be connected together ex-

ternally to guarantee accuracy

VREF (2)

The reference input voltage pin To maintain

accuracy the voltage at this pin should not

exceed the AVCC or DVCC by more than

50 mV or go below a35 VDC

VIN (1)

The analog input voltage pin To guarantee

accuracy the voltage at this pin should not

exceed VCC by more than 50 mV or go below

Vb by more than 50 mV

CS (10)

The Chip Select control input This input is

active low and enables the WR RD and S H

functions

RD (23)

The Read control input With both CS and RD

low the TRI-STATE output buffers are en-

abled and the INT output is reset high

WR (7)

The Write control input The conversion is

started on the rising edge of the WR pulse

when CS is low When this control line is

used the end of the analog input voltage ac-

quisition window is internally controlled by the

ADC12451

S H (11)

The sample and hold control input This con-

trol input can also be used to start a conver-

sion With CS low the falling edge of S H

starts the analog input acquisition window

The rising edge of S H ends the acquisition

window and starts a conversion

CLKIN (8)

The external clock input pin The typical clock

frequency range is 500 kHz to 60 MHz

CAL (9)

The Auto-Calibration control input

When

CAL is low the ADC12451 is reset and a cali-

bration cycle is initiated During the calibra-

tion cycle the values of the comparator offset

voltage and the mismatch errors in the ca-

pacitor reference ladder are determined and

stored in RAM These values are used to cor-

rect the errors during a normal cycle of AD

conversion

AZ (6)

The Auto-Zero control input With the AZ pin

held low during a conversion the ADC12451

goes into an auto-zero cycle before the actu-

al AD conversion is started This Auto-Zero

cycle corrects for the comparator offset volt-

age The total conversion time (tC)isin-

creased by 26 clock periods when Auto-Zero

is used

EOC (22)

The End-of-Conversion control output This

output is low during a conversion or a calibra-

tion cycle

INT (21)

The Interrupt control output This output goes

low when a conversion has been completed

and indicates that the conversion result is

available in the output latches Reading the re-

sult or starting a conversion or calibration cy-

cle will reset this output high

DB0DB8 -

The TRI-STATE output pins Twelve bit plus

sign output data access is accomplished using

DB7DB12

two successive RDs of one byte each high

(13 – 20)

byte first (DB8 – DB12) The data format used

is two’s complement sign bit extended with

DB12 the sign bit DB11 the MSB and DB0 the

LSB

20 Functional Description

The ADC12451 is a 12-bit plus sign AD converter with the

capability of doing Auto-Zero or Auto-Calibration routines to

minimize zero full-scale and linearity errors It is a succes-

sive-approximation AD converter consisting of a DAC

comparator and a successive-approximation register (SAR)

Auto-Zero is an internal calibration sequence that corrects

for the AD’s zero error caused by the comparator’s offset

voltage Auto-Cal is a calibration cycle that not only corrects

zero error but also corrects for full-scale and linearity errors

caused by DAC inaccuracies Auto-Cal minimizes the errors

of the ADC12451 without the need of trimming during its

fabrication An Auto-Cal cycle can restore the accuracy of

the ADC12451 at any time which ensures accuracy over

temperature and time

21 DIGITAL INTERFACE

On power up a calibration sequence should be initiated by

pulsing CAL low with CS and S H high To acknowledge the

CAL signal EOC goes low after the falling edge of CAL and

remains low during the calibration cycle of 1399 clock peri-

ods During the calibration sequence first the comparator’s

offset is determined then the capacitive DAC’s mismatch

error is found Correction factors for these errors are then

stored in internal RAM

A conversion is initiated by taking CS and WR low If AZ is

low an Auto-Zero cycle which takes approximately 26 clock

periods is inserted before the analog input is sampled and

the actual conversion is started AZ must remain low during

the complete conversion sequence After Auto-Zero the ac-

quisition opens and the analog input is sampled for appprox-

imately 7 clock periods If AZ is high the Auto-Zero cycle is

not inserted after the rising edge of WR In this case the

acquisition window opens when the ADC12451 completes a

conversion signaled by the rising edge of EOC At the end

of the acquisition window EOC goes low signaling that the

analog input is no longer being sampled and that the AD

successive approximation conversion has started

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