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AD7768BSTZ Datasheet(PDF) 16 Page - Analog Devices |
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AD7768BSTZ Datasheet(HTML) 16 Page - Analog Devices |
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16 / 99 page  AD7768/AD7768-4 Data Sheet Rev. A | Page 16 of 99 TIMING SPECIFICATIONS AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD; CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 5 and Table 6 for timing specifications at 1.8 V IOVDD. Table 3. Data Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit MCLK Master clock 1.15 34 MHz fMOD Modulator frequency Fast mode MCLK/4 Hz Median mode MCLK/8 Hz Eco mode MCLK/32 Hz t1 DRDY high time tDCLK = t8 + t9 tDCLK − 10% 28 ns t2 DCLK rising edge to DRDY rising edge 2 ns t3 DCLK rising to DRDY falling −3.5 0 ns t4 DCLK rise to DOUTx valid 1.5 ns t5 DCLK rise to DOUTx invalid −3 ns t6 DOUTx valid to DCLK falling 9.5 tDCLK/2 ns t7 DCLK falling edge to DOUTx invalid 9.5 tDCLK/2 ns t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns t8a = DCLK = MCLK/2 tMCLK = 1/MCLK tMCLK ns t8b = DCLK = MCLK/4 2 × tMCLK ns t8c = DCLK = MCLK/8 4 × tMCLK ns t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns t9a = DCLK = MCLK/2 tMCLK ns t9b = DCLK = MCLK/4 2 × tMCLK ns t9c = DCLK = MCLK/8 4 × tMCLK ns t10 MCLK rising to DCLK rising CMOS clock 30 ns t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on the AD7768-4 14 ns t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on the AD7768-4 0 ns t13 START low time 1 × tMCLK ns t14 MCLK to SYNC_OUT valid CMOS clock SYNC_OUT RETIME_EN bit disabled; measured from falling edge of MCLK 4.5 22 ns SYNC_OUT RETIME_EN bit enabled; measured from rising edge of MCLK 9.5 27.5 ns t15 SYNC_IN setup time CMOS clock 0 ns t16 SYNC_IN hold time CMOS clock 10 ns 1 These specifications are not production tested but are supported by characterization data at initial product release. Table 4. SPI Control Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit t17 SCLK period 100 ns t18 CS falling edge to SCLK rising edge 26.5 ns t19 SCLK falling edge to CS rising edge 27 ns t20 CS falling edge to data output enable 22.5 40.5 ns t21 SCLK high time 20 50 ns t22 SCLK low time 20 50 ns t23 SCLK falling edge to SDO valid 15 ns t24 SDO hold time after SCLK falling 7 ns t25 SDI setup time 0 ns t26 SDI hold time 6 ns t27 SCLK enable time 0 ns |
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