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AD9691 Datasheet(PDF) 63 Page - Analog Devices |
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AD9691 Datasheet(HTML) 63 Page - Analog Devices |
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63 / 72 page  Data Sheet AD9691 Rev. 0 | Page 63 of 72 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes DDC Function Registers (See the Digital Downconverters (DDCs) Section) 0x300 DDC sync control 0 0 0 DDC NCO soft reset 0 = normal operation 1 = reset 0 0 Synchronization mode (triggered by SYSREF±) 00 = disabled 01 = continuous 11 = one-shot 0x310 DDC 0 control Mixer select 0 = real mixer 1 = complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) Complex to real enable 0 = disabled 1 = enabled 0 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 0x311 DDC 0 input selection 0 0 0 0 0 Q input select 0 = Ch. A 1 = Ch. B 0 I input select 0 = Ch. A 1 = Ch. B 0x00 0x314 DDC 0 frequency LSB DDC 0 NCO FTW, Bits[7:0], twos complement 0x00 0x315 DDC 0 frequency MSB X X X X DDC 0 NCO FTW, Bits[11:8], twos complement 0x00 0x320 DDC 0 phase LSB DDC 0 NCO POW, Bits[7:0], twos complement 0x00 0x321 DDC 0 phase MSB X X X X DDC 0 NCO POW, Bits[11:8], twos complement 0x00 0x327 DDC 0 output test mode selection 0 0 0 0 0 Q output test mode enable 0 = disabled 1 = enabled from Channel B 0 I output test mode enable 0 = disabled 1 = enabled from Channel A 0x00 0x330 DDC 1 control Mixer select 0 = real mixer 1 = complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) Complex to real enable 0 = disabled 1 = enabled 0 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 0x331 DDC 1 input selection 0 0 0 0 0 Q input select 0 = Ch. A 1 = Ch. B 0 I input select 0 = Ch. A 1 = Ch. B 0x00 0x334 DDC 1 frequency LSB DDC 1 NCO FTW, Bits[7:0], twos complement 0x00 0x335 DDC 1 frequency MSB X X X X DDC 1 NCO FTW, Bits[11:8], twos complement 0x00 |
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