ADAV4601BSTZ datasheet(21/60 Pages) AD

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ADAV4601

Rev. B | Page 21 of 60

I2S Mode

Right-Justified (RJ) Mode

In I2S mode, the data is left-justified, MSB first, with the MSB

placed in the second BCLK period following the transition of

the LRCLK. A high-to-low transition of the LRCLK signifies the

beginning of the left channel data transfer, and a low-to-high

transition on the LRCLK signifies the beginning of the right

channel data transfer (see Figure 27).

In RJ mode, the data is right-justified, LSB last, with the LSB

placed in the last BCLK period preceding the transition of LRCLK.

A high-to-low transition of the LRCLK signifies the beginning

of the right-channel data transfer, and a low-to-high transition

on the LRCLK signifies the beginning of the left-channel data

transfer (see Figure 29).

Left-Justified (LJ) Mode

In LJ mode, the data is left-justified, MSB first, with the MSB

placed in the first BCLK period following the transition of the

LRCLK. A high-to-low transition of the LRCLK signifies the

beginning of the right-channel data transfer, and a low-to-high

transition on the LRCLK signifies the beginning of the left-

channel data transfer (see Figure 28).

LRCLK

BCLK

SDO0

MSB

LEFT CHANNEL

LSB

MSB

RIGHT CHANNEL

LSB

1 /FS

Figure 27. I2S Mode

LRCLK

BCLK

SDO0

LEFT CHANNEL

MSB

LSB

MSB

RIGHT CHANNEL

LSB

1 /FS

Figure 28. Left-Justified Mode

LRCLK

BCLK

SDO0

LEFT CHANNEL

MSB

LSB

MSB

RIGHT CHANNEL

LSB

1 /FS

Figure 29. Right-Justified Mode

ADAV4601BSTZ Datasheet(PDF) 21 Page - Analog Devices

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