CLC426 datasheet(5/8 Pages) NSC

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Supply Current Adjustment

The CLC426's supply current can be externally adjusted

downward from its nominal value to less than 2mA by

adding an optional resistor (Rp) between pin 8 and the

negative supply as shown in fig 2. The plot labeled "Open-

Loop Gain vs. Supply Current" illustrates the influence

that supply current has over the CLC426's open-loop

response. From the plot it is seen that the CLC426 can be

compensated for unity-gain stability by simply lowering

its supply current. Therefore lowering the CLC426's sup-

ply current effectively reduces its open-loop gain to the

point that there is adequate phase margin at unity gain

crossover. The plot labeled "Supply Current vs. Rp"

provides the means for selecting the value of Rp that

produces the desired supply current. The curve in the plot

represents nominal processing but a ±12% deviation over

process can be expected. The two plots labeled "Voltage

Noise vs. Supply Current" and "Current Noise vs. Supply

Current" illustrate the CLC426 supply current's effect over

its input-referred noise characteristics.

Driving Capacitive Loads

The CLC426 is designed to drive capacitive loads with the

addition of a small series resistor placed between the

output and the load as seen in fig. 3. Two plots located in

the Typical Performance section illustrate this technique

for both frequency domain and time domain applications.

The plot labeled "Frequency Response vs. Capacitive

Load" shows the CLC426's resulting AC response to

various capacitive loads. The values of Rs in this plot

were chosen to maximize the CLC426's AC response

(limited to

≤1dB peaking).

The second plot labeled "Settling Time vs. Capacitive

Load" provides the means for the selection of the value of

Rs which minimizes the CLC426's settling time. As seen

from the plot, for a given capacitive load Rs is chosen from

the curve labeled "Rs". The resulting settling time to

0.05% can then be estimated from the curve labeled "Ts

to 0.05%". The plot of fig. 4 shows the CLC426's pulse

response for various capacitive loads where Rs has been

chosen from the plot labeled "Settling Time vs. Capaci-

tive Load".

Faster Settling

The circuit of fig. 5 shows an alternative method for driving

capacitive loads that results in quicker settling times. The

small series-resistor, Rs, is used to decouple the CLC426's

open-loop output resistance, Rout, from the load capaci-

tance. The small feedback-capacitance, Cf, is used to

provide a high-frequency bypass between the output and

inverting input. The phase lead introduced by Cf compen-

sates for the phase lag due to CL and therefore restores

stability. The following equations provide values of Rs and

Cf for a given load capacitance and closed-loop amplifier

gain.

Eq. 1

Eq. 2

The plot in

fig. 6 shows

the result of the two methods of capacitive load driving

mentioned above while driving a 100pF||1k

Ω load.

Fig. 2

Fig. 4

Fig. 5

Fig. 3

where R

out

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Ω

Fig. 6

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