Application Discussion

Low Noise Design

Ultimate low noise performance from circuit designs using

the CLC428 requires the proper selection of

external resistors. By selecting appropriate low-valued

can achieve output noise that is approximately the

equivalent voltage input noise of 2.0 nV/

√Hz multiplied

by the desired gain (Av).

Each amplifier in the CLC428 has an equivalent

input noise resistance which is optimum for matching

source impedances of approximately 1k. Using a

transformer, any source can be matched to achieve the

lowest noise design.

For even lower noise performance than the CLC428,

consider the CLC425 or CLC426 at 1.05 and 1.6 nV/

√Hz,

respectively.

DC Bias Currents and Offset Voltages

Cancellation of the output offset voltage due to input bias

currents is possible with the CLC428. This is done by

making the resistance seen from the inverting and non-

inverting inputs equal. Once done, the residual output

offset voltage will be the input offset voltage (Vos) multi-

plied by the desired gain (Av). Comlinear Application Note

OA-7 offers several solutions to further reduce the output

offset.

Output and Supply Considerations

With ±5V supplies, the CLC428 is capable of a typical

output swing of ±3.8V

under a no-load condition.

Additional output swing is possible with slightly higher

supply voltages. For loads of less than 50

Ω, the output

swing will be limited by the CLC428’s output current

capability, typically 80mA.

Output settling time when driving capacitive loads can be

improved by the use of a series output resistor. See the

plot labeled "Settling Time vs. Capacitive Load" in the

Typical Performance section.

Layout

Proper power supply bypassing is critical to insure good high

frequency performance and low noise. De-coupling capaci-

tors of 0.1

µF should be place as close as possible to the

power supply pins. The use of surface mounted capacitors

is recommended due to their low series inductance.

A good high frequency layout will keep power supply and

ground traces away from the inverting input and output

pins. Parasitic capacitance from these nodes to ground

causes frequency response peaking and possible circuit

oscillation. See OA-15 for more information. National

suggests the CLC730038 (through-hole) or the CLC730036

(SOIC) dual op amp evaluation board as a guide for high

frequency layout and as an aid in device evaluation.

http://www.national.com

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