CLC428 datasheet(5/8 Pages) NSC

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Analog Delay Circuit (All-Pass Network)

The circuit in Figure 1 implements an all-pass network using

the CLC428. A wide bandwidth buffer (CLC111) drives the

circuit and provides a high input impedence for the source.

As shown in Figure 2, the circuit provides a

Figure 1

Figure 2

13.1ns delay (with R =40.2

Ω, C=47pF). Rf and Rg should

be of equal and low value for parasitic insensitive opera-

tion. The circuit gain is +1 and the delay is determined by

the following equations.

delay

Eq. 1

d =

360

;

Eq. 2

where Td is the delay of the op amp at AV=+1. The CLC428

provides a typical delay of 2.8ns at its -3dB point.

Full Duplex Digital or Analog Transmission

Simultaneous transmission and reception of analog or

digital signals over a single coaxial cable or twisted-pair

line can reduce cabling requirements. The CLC428's wide

bandwidth and high common-mode rejection in a differen-

tial amplifier configuration allows full duplex transmission

of video, telephone, control and audio signals.

In the circuit shown in Figure 3, one of the CLC428's amps

is used as a "driver" and the other as a difference

"receiver" amplifier. The output impedance of the "driver"

is essentially zero. The two R's are chosen to match the

characteristic impedance of the transmission line. The

"driver" op amp gain can be selected for unity or greater.

Receiver amplifier A2 (B2) is connected across R and

forms differential amplifier for the signals transmitted by

driver A1 (B1). If the coax cable is lossless and Rf equals

Rg, receiver A2 (B2) will then reject the signals from driver

Figure 3

A1 (B1) and pass the signals from driver B1 (A1). The

output of the receiver amplifier will be:

out

a f

=−

HGG

KJJ

HGG

KJJ

Eq. 3

Care must be given to layout and component placement to

maintain a high frequency common-mode rejection. The

plot of Figure 4 shows the simultaneous reception of

signals transmitted at 1MHz and 10MHz.

Figure 4

Five Decade Integrator

A composite integrator, as shown in Figure 5, uses the

CLC428 dual op amp to increase the circuits' usable

frequency range of operation. The transfer function of this

circuit is:

Vdt

Eq. 4

Figure 5

A resistive divider made from the 143

Ω and 60.4Ω

resistors was chosen to reduce the loop-gain and stabilize

the network. The CLC428 composite integrator provides

integration over five decades of operation. R and C set the

integrator's gain. Figure 6 shows the frequency and phase

response of the circuit in Figure 5 with R = 44.2

Ω and

C = 360pF.

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