CLC428 datasheet(6/8 Pages) NSC

6 / 8 page

Figure 6

Positive Peak Detector

The CLC428's dual amplifiers can be used to implement a

unity-gain peak detector circuit as shown in Figure 7.

Figure 7

The acquisition speed of this circuit is limited by the

dynamic resistance of the diode when charging Chold. A

plot of the of the circuit's performance is shown in Figure

8 with a 1MHz sinusoidal input.

Figure 8

A current source, built around Q1, provides the necessary

bias current for the second amplifier and prevents satura-

tion when power is applied. The resistor, R, closes the loop

while diode D2 prevents negative saturation when Vin is

less than Vc. A MOS-type switch (not shown) can be used

to reset the capacitor's voltage.

The maximum speed of detection is limited by the delay

of the op amps and the diodes. The use of Schottky diodes

will provide faster response.

Adjustable or Bandpass Equalizer

A "boost" equalizer can be made with the CLC428 by

summing a bandpass response with the input signal, as

shown in Figure 9.

Figure 9

The overall transfer function is shown in Eq. 5.

s2Q

out

KJ ++ −

Eq. 5

To build a boost circuit, use the design equations Eq. 6 and

Eq. 7.

,2C R ||R

ωω

Eq. 6,7

Select R2 and C using Eq. 6. Use reasonable values for

high frequency circuits - R2 between 10Ω and 5kΩ, C

between 10pF and 2000pF. Use Eq. 7 to determine the

parallel combination of Ra and Rb. Select Ra and Rb by

either the 10

Ω to 5kΩ criteria or by other requirements

based on the impedance Vin is capable of driving. Finish

the design by determining the value of K from Eq. 8.

Peak Gain

out

−

ch 2

Eq. 8

Figure 10 shows an example of the response of the circuit

of Figure 9, where fo is 2.3MHz. The component values

are as follows: Ra =2.1kΩ, Rb =68.5Ω, R2 =4.22kΩ, R

=500

Ω, KR =50Ω, C =120pF.

Figure 10

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