TTP239

2016/3/7

Page 9 of 16

Version：1.1

2-wires serial interface mode timing please see below.

The D0~D7 correspond to data of the TP0~7.

7-1-1 When SAHL=0：Set active-high

T_resp

Tout

DV

DV

Ts

Ts

Ts

D0

D1

C_1

C_0

D0

D1

C_1

C_0

SDO

SCL

F_SCL

D7

D6

D5

D4

D3

D2

C_7

C_6

C_5

C_4

C_3

C_2

Figure 7-1-1：The timing for active-high

7-1-2 When SAHL=1：Set active-low

T_resp

Tout

DV

DV

Ts

Ts

Ts

D0

D1

C_1

C_0

D0

D1

C_1

C_0

F_SCL

D7

D6

D5

D4

D3

D2

C_7

C_6

C_5

C_4

C_3

C_2

SDO

SCL

Figure 7-1-2：The timing for active-low

The parameters for figure 7-1-1~2：

Parameter

Min.

Typ.

Max.

Unit

DV(Time out)

-

2

-

ms

Ts

200

-

-

ns

Tout

-

2

-

ms

T_resp

-

16

-

ms

F_SCL

1K

-

512K

Hz

Note：

(1) When any data of the TP0~TP7 change, the SDO pin output DV signal, the time out of DV

signal is about 2msec. But other device can not wait that the DV signal time is over, after it

detect the DV signal, and then can give the clock signal to the TTP239 by the SCL pin at the

duration of DV signal. When the TTP239 detect the first clock edge changing, and the DV

signal is over, and the SDO pin change to output the data of TP0~TP7.

(2) The parameter Ts is data set-up time, it means that the data change time for SDO pin.