COP888EB datasheet(61/75 Pages) NSC

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Baud Clock Generation (Continued)

TABLE 16. Baud Rate Divisors

(1.8432 MHz Prescaler Output)

Baud

Baud Rate

Rate

Divisor −1 (N-1)

110 (110.03)

1046

134.5 (134.58)

855

150

767

300

383

600

191

1200

1800

2400

3600

4800

7200

9600

19200

38400

Note: The entries in

Table 16 assume a prescaler output of 1.8432 MHz. In

the asynchronous mode the baud rate could be as high as 625k.

As an example, considering the Asynchronous Mode and a

CKI clock of 4.608 MHz, the prescaler factor selected is:

4.608/1.8432 = 2.5

The 2.5 entry is available in

Table 15. The 1.8432 MHz pres-

caler output is then used with proper Baud Rate Divisor

(

Table 1) to obtain different baud rates. For a baud rate of

19200 e.g., the entry in

Table 16 is 5.

N−1=5(N−1isthe value from

Table 16)

N=6(Nisthe Baud Rate Divisor)

Baud Rate = 1.8432 MHz/(16 x 6) = 19200

The divide by 16 is performed because in the asynchronous

mode, the input frequency to the USART is 16 times the

baud rate. The equation to calculate baud rates is given be-

low.

The actual Baud Rate may be found from:

BR = Fc/(16XNXP)

Where:

BR is the Baud Rate

Fc is the CKI frequency

N is the Baud Rate Divisior (

Table 16).

P is the Prescaler Divide Factor selected by the value in the

Prescaler Select Register (

Table 15)

Note: In the Synchronous Mode, the divisor 16 is replaced by two.

Example:

Asynchronous Mode:

Crystal Frequency=5MHz

Desired baud rate = 9600

Using the above equationNXP can be calculated first.

NxP =(5X10

6)/(16 x 9600) = 32.552

Now 32.552 is divided by each Prescaler Factor (

Table 2)to

obtain a value closet to an integer. This factor happens to be

6.5 (P = 6.5).

N = 32.552/6.5 = 5.008 (N = 5)

The programmed value (from

Table 10) should be 4 (N −1).

Using the above values calculated for N and P:

BR=(5x106)/(16x5x 6.5) = 9615.384

% error = (9615.385 − 9600)/9600 * 100 = 0.16

Effect of HALT/IDLE

The USART logic is reinitialized when either the HALT or

IDLE modes are entered. This reinitialization sets the TBMT

flag and resets all read only bits in the USART control and

status registers. Read/Write bits remain unchanged. The

Transmit Buffer (TBUF) is not affected, but the Transmit Shift

RBUF and RSFT are not affected.

The device will exit from the HALT/IDLE modes when the

Start bit of a character is detected at the RDX (L3) pin. This

feature is obtained by using the Multi-Input Wakeup scheme

provided on the device.

Before entering the HALT or IDLE modes the user program

must select the Wakeup source to be on the RXD pin. This

selection is done by setting bit 3 of WKEN (Wakeup Enable)

high to low transition. This is done via the WKEDG register.

(Bit 3 is one.)

If the device is halted and crystal oscillator is used, the

Wakeup signal will not start the chip running immediately be-

cause of the finite start up time requirement of the crystal os-

cillator. The idle timer (T0) generates a fixed (256 t

c) delay to

ensure that the oscillator has indeed stabilized before allow-

ing the device to execute code. The user has to consider this

delay when data transfer is expected immediately after exit-

ing the HALT mode.

Diagnostic

Bits CHL0 and CHL1 in the ENU register provide a loopback

feature for diagnostic testing of the USART. When these bits

are set to one, the following occur: The receiver input pin

(RDX) is internally connected to the transmitter output pin

(TDX); the output of the Transmitter Shift Register is “looped

back” into the Receive Shift Register input. In this mode,

data that is transmitted is immediately received. This feature

allows the processor to verify the transmit and receive data

paths of the USART.

Note that the framing format for this mode is the nine bit for-

mat; one Start bit, nine data bits, and 7/8, one or two Stop

bits. Parity is not generated or verified in this mode.

Attention Mode

The USART Receiver section supports an alternate mode of

operation, referred to as ATTENTION Mode. This mode of

operation is selected by the ATTN bit in the ENUR register.

The data format for transmission must also be selected as

having nine Data bits and either 7/8, one or two Stop bits.

The ATTENTION mode of operation is intended for use in

networking the device with other processors, Typically in

such environments the messages consists of device ad-

dresses, indicating which of several destinations should re-

ceive them, and the actual data. This Mode supports a

scheme in which addresses are flagged by having the ninth

bit of the data field set to a 1. If the ninth bit is reset to a zero

the byte is a Data byte.

While in ATTENTION mode, the USART monitors the com-

munication flow, but ignores all characters until an address

character is received. Upon receiving an address character,

the USART signals that the character is ready by setting the

RBFL flag, which in turn interrupts the processor if USART

Receiver interrupts are enabled. The ATTN bit is also cleared

COP888EB Datasheet(PDF) 61 Page - National Semiconductor (TI)

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