COP888GD datasheet(15/42 Pages) NSC

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CONTROL REGISTERS (Continued)

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

T3CNTRL Register (Address X'00B6)

T3C3

T3C2

T3C1

T3C0

T3PNDA

T3ENA

T3PNDB

T3ENB

Bit 7

Bit 0

The T3CNTRL control register contains the following bits:

T3C3

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C1

Timer T3 mode control bit

T3C0

Timer

Start/Stop

control

timer

modes 1 and 2, T3 Underflow Interrupt Pend-

ing Flag in timer mode 3

T3PNDA

Timer T3 Interrupt Pending Flag (Autoreload

RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDB

Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENB

Timer T3 Interrupt Enable for Timer Underflow

or T3B Input capture edge

Timers

The device contains a very versatile set of timers (T0, T1,

T2, T3). All timers and associated autoreload/capture regis-

ters power up containing random data.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t

c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

j Exit out of the Idle Mode (See Idle Mode description)

j WATCHDOG logic (See WATCHDOG description)

j Start up delay out of the HALT mode

Figure 8 is a functional block diagram showing the structure

of the IDLE Timer and its associated interrupt logic.

Bits 11 through 15 of the ITMR register can be selected for

triggering the IDLE Timer interrupt. Each time the selected

bit underflows (every 4k, 8k, 16k, 32k or 64k instruction

cycles), the IDLE Timer interrupt pending bit T0PND is set,

thus generating an interrupt (if enabled), and bit 6 of the Port

G data register is reset, thus causing an exit from the IDLE

mode if the device is in that mode.

In order for an interrupt to be generated, the IDLE Timer in-

terrupt enable bit T0EN must be set, and the GIE (Global In-

terrupt Enable) bit must also be set. The T0PND flag and

T0EN bit are bits 5 and 4 of the ICNTRL register, respec-

tively. The interrupt can be used for any purpose. Typically, it

is used to perform a task upon exit from the IDLE mode. For

more information on the IDLE mode, refer to the Power Save

Modes section.

The Idle Timer period is selected by bits 0–2 of the ITMR

should not be used as software flags.

TABLE 3. Idle Timer Window Length

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

(Instruction Cycles)

4,096

8,192

16,384

32,768

65,536

The ITMR is cleared on Reset and the Idle Timer period is re-

set to 4,096 instruction cycles.

ITMR Register (Address X’0xCF)

Reserved

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 0

Any time the IDLE Timer period is changed there is the pos-

sibility of generating a spurious IDLE Timer interrupt by set-

ting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before at-

tempting to synchronize operation to the IDLE Timer.

COP888GD Datasheet(PDF) 15 Page - National Semiconductor (TI)

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