COP888GD datasheet(16/42 Pages) NSC

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Timers (Continued)

TIMER T1, TIMER T2 AND TIMER T3

The device has a set of three powerful timer/counter blocks,

T1, T2 and T3. The associated features and functioning of a

timer block are described by referring to the timer block Tx.

Since the three timer blocks, T1, T2 and T3 are identical, all

comments are equally applicable to any of the three timer

blocks.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention. The

user only has to define the parameters of the PWM signal

(ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the timer Tx counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Figure 9 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

DS100076-17

FIGURE 8. Functional Block Diagram for Idle Timer T0

COP888GD Datasheet(PDF) 16 Page - National Semiconductor (TI)

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