COP888GD datasheet(17/42 Pages) NSC

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Timers (Continued)

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB con-

trol flag is set. The occurrence of a positive edge on the TxB

input pin is latched into the TxPNDB flag.

Figure 10 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the TxA pin is being

used as the counter input clock.

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the in-

put capture mode.

In this mode, the timer Tx is constantly running at the fixed t

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag Tx-

ENA allows the interrupt on TxA to be either enabled or dis-

abled. Setting the TxENA flag enables interrupts to be gener-

ated when the selected trigger condition occurs on the TxA

pin. Similarly, the flag TxENB controls the interrupts from the

TxB pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Figure 11 shows a block diagram of the timer in Input Cap-

ture mode.

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

DS100076-10

FIGURE 9. Timer in PWM Mode

DS100076-11

FIGURE 10. Timer in External Event Counter Mode

DS100076-12

FIGURE 11. Timer in Input Capture Mode

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