COP8ACC7 datasheet(19/40 Pages) NSC

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Multi-Input Wakeup (Continued)

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT 5, WKEN

; Disable MIWU

SBIT 5, WKEDG

; Change edge polarity

RBIT 5, WKPND

; Reset pending flag

SBIT 5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid wakeup condi-

tions. After the selected L port bits have been changed from

output to input but before the associated WKEN bits are en-

abled, the associated edge select bits in WKEDG should be

set or reset for the desired edge selects, followed by the as-

sociated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user must

clear the pending flags before attempting to enter the HALT

mode.

WKEN, WKPND and WKEDG are all read/write registers,

and are cleared at reset.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

Analog Function Block

This device contains an analog function block with the intent

to provide a function which allows for single slope, low cost,

A/D conversion of up to 6 channels.

CMPSL REGISTER (ADDRESS X’00B7)

CMPT2B

CMPISEL2

CMPISEL1

CMPISEL0

CMPOE

CSEN

CMPEN

CMPNEG

Bit 7

Bit 0

The CMPSL register contains the following bits:

CMPT2B

Selects the “High Speed 16-bit Capture

Timer” input to be driven directly by the

comparator output. If the comparator is dis-

abled (CMPEN=0), this function is dis-

abled, i.e. the Capture Timer input is con-

nected to GND.

CMPISEL0/1/2 Will select one of seven possible sources

(I0/I2/I3/I4/I5/I6/internal reference) as a

positive input to the comparator (see

Table

4 for more information)

CMPOE

Enables the comparator output to either pin

I3 or pin I7 (“1”=enable) depending on the

value of CMPISEL0/1/2.

CSEN

Enables

the

internal

constant

current

source. This current source provides a

nominal 20 µA constant current at the I1

pin. This current can be used to ensure a

linear charging rate on an external capaci-

tor. This bit has no affect and the current

source is disabled if the comparator is not

enabled (CMPEN=0).

CMPEN

Enable the comparator (“1” = enable)

CMPNEG

Will drive I1 to a low level. This bit can be

used to discharge an external capacitor.

This bit is disabled if the comparator is not

enabled (CMPEN=0).

The Comparator Select Register is cleared on RESET (the

comparator is disabled). To save power the program should

also disable the comparator before the µC enters the HALT/

IDLE modes. Disabling the comparator will turn off the con-

stant current source and the V

CC/2 reference, disconnect the

comparator output from the Capture Timer input and pin I3/I7

and remove the low on I1 caused by CMPNEG.

It is often useful for the user’s program to read the result of

a comparator operation. Since I1 is always selected to be

COMPIN — when the comparator is enabled (CMPEN=1),

the comparator output can be read internally by reading bit 1

(CMPRD) of register PORTI (RAM address 0xD7).

The following table lists the comparator inputs and outputs

versus the value of the CMPISEL0/1/2 bits. The output will

only be driven if the CMPOE bit is set to 1.

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