COP8ACC7 datasheet(21/40 Pages) NSC

21 / 40 page

Interrupts (Continued)

Each of the 8 maskable inputs has a fixed arbitration ranking

and vector.

Figure 14 shows the Interrupt Block Diagram.

MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

A maskable interrupt condition triggers an interrupt under the

following conditions:

The enable bit associated with that interrupt is set.

The GIE bit is set.

The device is not processing a non-maskable interrupt.

(If a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any pre-

vious occurrences of the interrupt should be ignored, the as-

sociated pending bit must be reset to zero prior to enabling

the interrupt. Otherwise, the interrupt may be simply en-

abled; if the pending bit is already set, it will immediately trig-

ger an interrupt. A maskable interrupt is active if its associ-

ated enable and pending bits are set.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending in-

terrupt is acknowledged.

At the start of interrupt acknowledgment, the following ac-

tions occur:

The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

The address of the instruction about to be executed is

pushed onto the stack.

The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

DS012869-15

FIGURE 14. Interrupt Block Diagram

COP8ACC7 Datasheet(PDF) 21 Page - National Semiconductor (TI)

COP8ACC7 Datasheet(HTML) 21 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL