M68SDIL datasheet(93/432 Pages) MOTOROLA

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Bus Control and Input/Output

Registers

68HC(9)12D60 — Rev 4.0

Advance Information

MOTOROLA

Bus Control and Input/Output

In normal expanded modes, the reset vector is located in external

memory. The DBE and E clock are required for de-multiplexing address

and data, but LSTRB and R/W are only needed by the system when

there are external writable resources. Therefore in normal expanded

modes, only the DBE and E clock are configured for their alternate bus

control functions and the other bits of port E are configured for general-

purpose I/O. If the normal expanded system needs any other bus-control

signals, PEAR would need to be written before any access that needed

the additional signals.

In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and R/W

are configured as bus-control signals.

In peripheral mode, the PEAR register is not accessible for reads or

writes. However, the CGMTE control bit is reset to one to configure PE6

as a test output from the PLL module.

NDBE — No Data Bus Enable

Normal: write once; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE7 is used for DBE, external control of data enable on

memories, or inverted E clock.

1 = PE7 is the CAL function if CALE bit is set in PEAR register or

general-purpose I/O.

NDBE controls the use of the DBE pin of Port E. The NDBE bit has no

effect in Single Chip or Peripheral Modes. The associated pin will

default to the CAL function if the CALE bit is set in PEAR register or

otherwise to an I/O.

CGMTE — Clock Generator Module Testing Enable

Normal: write never; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE6 is general-purpose I/O or pipe output.

1 = PE6 is a test signal output from the CGM module (no effect in

single chip or normal expanded modes). PIPOE = 1 overrides

this function and forces PE6 to be a pipe status output signal.

Freescale Semiconductor, Inc.

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M68SDIL Datasheet(PDF) 93 Page - Motorola, Inc