BCM4354 datasheet(73/192 Pages) CYPRESS

73 / 192 page

PCI Express Interface

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 72

Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication

between the host and BCM4354 device. The transmit side processes outbound packets whereas the receive

side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for

transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to

indicate the packet type and any other optional fields.

Figure 29: PCI Express Layer Model

Transaction Layer Interface

The PCIe core employs a packet-based protocol to transfer data between the host and BCM4354 device,

delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The

Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs).

TLP structure contains header, data payload, and End-to-End CRC (ECRC) fields, which are used to

communicate transactions, such as read and write requests and other events.

A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication

between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.

Data Link Layer

The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its

primary responsibility is to provide reliable, efficient mechanism for the exchange of TLPs between two directly

connected components on the link. Services provided by the data link layer include data exchange, initialization,

error detection and correction, and retry services.

Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the

mechanism used to transfer link management information between data link layers of the two directly connected

components on the link, including TLP acknowledgement, power management, and flow control.

Transaction

Layer

Data Link

Layer

Logical Subblock

Electrical Subblock

Physical Layer

Transaction

Layer

Data Link

Layer

Logical Subblock

Electrical Subblock

Physical Layer

HW/SW Interface

BCM4354 Datasheet(PDF) 73 Page - Cypress Semiconductor

BCM4354 Datasheet(HTML) 73 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL