BCM4354 datasheet(170/192 Pages) CYPRESS

Part #	BCM4354

Description	Single-Chip 5G Wi-Fi IEEE 802.11ac 2횞2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

PDF	192 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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170 / 192 page

SDIO Timing

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 169

SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 38 and Table 52.

Figure 38: SDIO Bus Timing (High-Speed Mode)

Table 52: SDIO Bus Timinga Parameters (High-Speed Mode)

a. Timing is based on CL

 40pF load on CMD and Data.

Parameter

Symbol

Minimum

Typical

Maximum Unit

SDIO CLK (all values are referred to minimum VIH and maximum VILb)

b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.

Frequency – Data Transfer Mode

fPP

–

MHz

Frequency – Identification Mode

fOD

–

400

kHz

Clock low time

tWL

7––ns

Clock high time

tWH

7––ns

Clock rise time

tTLH

––3ns

Clock low time

tTHL

––3ns

Inputs: CMD, DAT (referenced to CLK)

–––––

Input setup Time

tISU

6––ns

Input hold Time

tIH

2––ns

Outputs: CMD, DAT (referenced to CLK)

–––––

Output delay time – Data Transfer Mode

tODLY

–

Output hold time

tOH

2.5

–

Total system capacitance (each line)

–

tWL

tWH

fPP

tTHL

tISU

tTLH

tIH

tODLY

Input

Output

50% VDD

tOH

SDIO_CLK

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