BCM4354 datasheet(176/192 Pages) CYPRESS

Part #	BCM4354

Description	Single-Chip 5G Wi-Fi IEEE 802.11ac 2횞2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

PDF	192 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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176 / 192 page

SDIO Timing

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 175

Data Timing, DDR50 Mode

Figure 45: SDIO Data Timing (DDR50 Mode)

Table 58: SDIO Bus Timing Parameters (DDR50 Mode)

Parameter

Symbol

Minimum

Maximum

Unit

Comments

Input CMD

Input setup time

tISU

6–ns

CCARD < 10 pF (1 Card)

Input hold time

tIH

0.8

–

CCARD < 10 pF (1 Card)

Output CMD

Output delay time

tODLY

–13.7

CCARD < 30 pF (1 Card)

Output hold time

tOH

1.5

–

CCARD < 15 pF (1 Card)

Input DAT

Input setup time

tISU2x

3–ns

CCARD < 10 pF (1 Card)

Input hold time

tIH2x

0.8

–

CCARD < 10 pF (1 Card)

Output DAT

Output delay time

tODLY2x

–7.5

CCARD < 25 pF (1 Card)

Output hold time

tODLY2x

1.5

–

CCARD < 15 pF (1 Card)

tISU2x

SDIO_CLK

DAT[3:0]

input

FPP

tIH2x

tISU2x

tIH2x

Invalid

Data

tODLY2x

(min)

tODLY2x

(min)

tODLY2x (max)

DAT[3:0]

output

In DDR50 mode, DAT[3:0] lines are sampled on both edges of

the clock (not applicable for CMD line)

Available timing

window for card

output transition

Available timing

window for host to

sample data from card

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