COP8SCR9 datasheet(44/80 Pages) NSC

44 / 80 page

13.0 Power Saving Features

(Continued)

associated WKEN bit should be reset, followed by the edge

select change in WKEDG. Next, the associated WKPND bit

should be cleared, followed by the associated WKEN bit

being re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT

5, WKEN

; Disable MIWU

SBIT

5, WKEDG

; Change edge polarity

RBIT

5, WKPND

; Reset pending flag

SBIT

5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wake-up/Interrupt, a

safety procedure should also be followed to avoid wake-up

conditions. After the selected L port bits have been changed

from output to input but before the associated WKEN bits are

enabled, the associated edge select bits in WKEDG should

be set or reset for the desired edge selects, followed by the

associated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for Multi-

Input Wake-up is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the

corresponding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wake-up bit is

both enabled and pending. Consequently, the user must

clear the pending flags before attempting to enter the HALT

mode.

WKEN and WKEDG are all read/write registers, and are

cleared at reset. WKPND register contains random value

after reset.

14.0 USART

The device contains a full-duplex software programmable

USART. The USART (Figure 22) consists of a transmit shift

isters, as follows: a transmit buffer register (TBUF), a re-

ceiver buffer register (RBUF), a USART control and status

(ENUR), a USART interrupt and clock source register

(ENUI), a prescaler select register (PSR) and baud (BAUD)

receive functions; this register also determines the length of

the data frame (7, 8 or 9 bits), the value of the ninth bit in

transmission, and parity selection bits. The ENUR register

flags framing, data overrun, parity errors and line breaks

while the USART is receiving.

Other functions of the ENUR register include saving the

ninth bit received in the data frame, enabling or disabling the

USART’s attention mode of operation and providing addi-

tional receiver/transmitter status information via RCVG and

XMTG bits. The determination of an internal or external clock

source is done by the ENUI register, as well as selecting the

number of stop bits and enabling or disabling transmit and

receive interrupts. A control flag in this register can also

select the USART mode of operation: asynchronous or

synchronous.

COP8SCR9 Datasheet(PDF) 44 Page - National Semiconductor (TI)

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