COP8SCR9 datasheet(57/80 Pages) NSC

57 / 80 page

16.0 WATCHDOG/Clock Monitor

The devices contain a user selectable WATCHDOG and

clock monitor. The following section is applicable only if the

WATCHDOG feature has been selected in the Option regis-

ter. The WATCHDOG is designed to detect the user program

getting stuck in infinite loops resulting in loss of program

control or “runaway” programs.

The WATCHDOG logic contains two separate service win-

dows. While the user programmable upper window selects

the WATCHDOG service time, the lower window provides

protection against an infinite program loop that contains the

WATCHDOG service instruction. The WATCHDOG uses the

Idle Timer (T0) and thus all times are measured in Idle Timer

Clocks.

The Clock Monitor is used to detect the absence of a clock or

a very slow clock below a specified rate on t

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 20 shows the WDSVR register.

TABLE 20. WATCHDOG Service Register (WDSVR)

Window

Select

Key Data

Clock

Monitor

01100

654321

The lower limit of the service window is fixed at 2048 Idle

Timer Clocks. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 21 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

TABLE 21. WATCHDOG Service Window Select

WDSVR

Bit 7

WDSVR

Bit 6

Clock

Monitor

Bit 0

Service Window

for High Speed Mode

(Lower-Upper Limits)

Service Window

for Dual Clock & Low Speed

Modes

(Lower-Upper Limits)

2048-8k t

C Cycles

2048-8k Cycles of 32 kHz Clk

2048-16k t

C Cycles

2048-16k Cycles of LS 32 kHz Clk

2048-32k t

C Cycles

2048-32k Cycles of LS 32 kHz Clk

2048-64k t

C Cycles

2048-64k Cycles of LS 32 kHz Clk

Clock Monitor Disabled

Clock Monitor Enabled

16.1 CLOCK MONITOR

The Clock Monitor aboard the device can be selected or

deselected under program control. The Clock Monitor is

guaranteed not to reject the clock if the instruction cycle

clock (1/t

C) is greater or equal to 5 kHz. This equates to a

clock input rate on the selected oscillator of greater or equal

to 25 kHz.

16.2 WATCHDOG/CLOCK MONITOR OPERATION

The WATCHDOG is enabled by bit 2 of the Option register.

When this Option bit is 0, the WATCHDOG is enabled and

pin G1 becomes the WATCHDOG output with a weak pull-

up.

The WATCHDOG and Clock Monitor are disabled during

reset. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR

the WATCHDOG service window (ii) enabling or disabling of

the Clock Monitor. Hence, the first write to WDSVR Register

involves selecting or deselecting the Clock Monitor, select

the WATCHDOG service window and match the WATCH-

DOG key data. Subsequent writes to the WDSVR register

will compare the value being written by the user to the

WATCHDOG service window value, the key data and the

Clock Monitor Enable (all bits) in the WDSVR Register. Table

22 shows the sequence of events that can occur.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The

WATCHDOG may not be serviced more than once in every

lower limit of the service window.

When jumping to the boot ROM for ISP and virtual E2

operations, the hardware will disable the lower window error

and perform an immediate WATCHDOG service. The ISP

routines will service the WATCHDOG within the selected

upper window. The ISP routines will service the WATCH-

DOG immediately prior to returning execution back to the

user’s code in flash. Therefore, after returning to flash

memory, the user can service the WATCHDOG anytime

following the return from boot ROM, but must service it within

the selected upper window to avoid a WATCHDOG error.

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low. The WDOUT pin has a weak pull-up in the inactive

state. Upon triggering the WATCHDOG, the logic will pull the

WDOUT (G1) pin low for an additional 16–32 cycles after the

signal level on WDOUT pin goes below the lower Schmitt

COP8SCR9 Datasheet(PDF) 57 Page - National Semiconductor (TI)

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