COP8SCR9 datasheet(59/80 Pages) NSC

59 / 80 page

16.0 WATCHDOG/Clock Monitor

(Continued)

turn will cause the program to return to address 7FFF Hex.

The Option Register is located at this location and, when

accessed by an instruction fetch, will respond with an INTR

instruction (all 0’s) to generate a software interrupt, signalling

an illegal condition on overpop of the stack.

Thus, the chip can detect the following illegal conditions:

Executing from undefined Program Memory

Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

17.0 MICROWIRE/PLUS

MICROWIRE/PLUS is a serial SPI compatible synchronous

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with MICROWIRE/PLUS

or SPI peripherals (i.e. A/D converters, display drivers,

EEPROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE/PLUS or SPI interface. It consists of

an 8-bit serial shift register (SIO) with serial data input (SI),

serial data output (SO) and serial shift clock (SK). Figure 29

shows a block diagram of the MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS

arrangement with the internal clock source is called the

Master

mode

operation.

Similarly,

operating

the

MICROWIRE/PLUS arrangement with an external shift clock

is called the Slave mode of operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the

master mode, the SK clock rate is selected by the two bits,

SL0 and SL1, in the CNTRL register. Table 23 details the

different clock rates that may be selected.

TABLE 23. MICROWIRE/PLUS

Master Mode Clock Select

SL1

SL0

SK Period

2xt

4xt

8xt

Where tC is the instruction cycle clock

17.1 MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 29 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

Warning:

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

Setting the BUSY flag when the input SK clock is in the

active phase while in the MICROWIRE/PLUS is in the slave

mode may cause the current SK clock for the SIO shift

be set when the input SK clock is in the idle phase.

17.1.1 MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE/

PLUS Master always initiates all data exchanges. The MSEL

bit in the CNTRL register must be set to enable the SO and

SK functions onto the G Port. The SO and SK pins must also

be selected as outputs by setting appropriate bits in the Port

G configuration register. In the slave mode, the shift clock

stops after 8 clock pulses. Table 24 summarizes the bit

settings required for Master mode of operation.

17.1.2 MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and

resetting the appropriate bits in the Port G configuration

the Slave mode of operation.

TABLE 24. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

Operation

Config. Bit

Fun.

Int.

MICROWIRE/PLUS

Master

TRI-

Int.

MICROWIRE/PLUS

STATE

Master

Ext.

MICROWIRE/PLUS

Slave

TRI-

Ext.

MICROWIRE/PLUS

STATE

Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

COP8SCR9 Datasheet(PDF) 59 Page - National Semiconductor (TI)

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