®

11

PCM1721

REGISTER 2 (A1 = 1, A0 = 0)

B15 B14 B13 B12 B11 B10 B9 B8

B7

B6 B5

B4

B3

B2

B1

B0

res res res

res res A1

A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE

Register 2 is used to control soft mute, de-emphasis, opera-

tion enable, input resolution, and output format. Bit 0 is used

for soft mute: a “HIGH” level on bit 0 will cause the output

to be muted (this is ramped down in the digital domain, so

no “click” is audible). Bit 1 is used to control de-emphasis.

A “LOW” level on bit 1 disables de-emphasis, while a

“HIGH” level enables de-emphasis.

Bit 2, (OPE) is used for operational control. Table V illus-

trates the features controlled by OPE.

SOFTWARE MODE

DATA INPUT

DAC OUTPUT

INPUT

Zero

Enabled

Other

Enabled

Zero

Controlled by IZD

Enabled

Other

Normal

Enabled

OPE = 1

OPE = 0

TABLE V. Operation Enable (OPE) Function.

Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.

The output of PCM1721 can be programmed for 16 different

states, as shown in Table VIII.

PL0

PL1

PL2

PL3

Lch OUTPUT

Rch OUTPUT

NOTE

0

0

0

0

MUTE

MUTE

MUTE

0

0

0

1

MUTE

R

0

0

1

0

MUTE

L

0

0

1

1

MUTE

(L + R)/2

0

1

0

0

R

MUTE

0

101

R

R

0

1

1

0

R

L

REVERSE

0

1

1

1

R

(L + R)/2

1

0

0

0

L

MUTE

1

0

0

1

L

R

STEREO

1

010

L

L

1

0

1

1

L

(L + R)/2

1

1

0

0

(L + R)/2

MUTE

1

1

0

1

(L + R)/2

R

1

1

1

0

(L + R)/2

L

1

1

1

1

(L + R)/2

(L + R)/2

MONO

OPE controls the operation of the DAC: when OPE is

“LOW”, the DAC will convert all non-zero input data. If the

input data is continuously zero for 65, 536 cycles of BCKIN,

the output will be forced to zero only if IZD is “HIGH”.

When OPE is “HIGH”, the output of the DAC will be forced

to bipolar zero, irrespective of any input data.

IZD = 1

IZD = 0

DATA INPUT

DAC OUTPUT

Zero

Other

Normal

Zero

Other

Normal

TABLE VI. Infinite Zero Detection (IZD) Function.

RSTB = “HIGH”

RSTB = “LOW”

SOFTWARE

MODE

DATA INPUT

DAC OUTPUT

INPUT

Zero

Controlled by OPE and IZD

Enabled

Other

Controlled by OPE and IZD

Enabled

Zero

Disabled

Other

Disabled

TABLE VII. Reset (RSTB) Function.

NOTE: (1)

∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to

output amplifier.

Bits 3 (IW0) and 4 (IW1) are used to determine input word

resolution. PCM1721 can be set up for input word resolu-

tions of 16, 20, or 24 bits:

Bit 4 (IW1)

Bit 3 (IW0)

Input Resolution

0

0

16-bit Data Word

0

1

20-bit Data Word

1

0

24-bit Data Word

0

0

Reserved

TABLE VIII. Programmable Output Format.

REGISTER 3 (A1 = 1, A0 = 1)

B15 B14 B13 B12 B11 B10 B9

B8

B7 B6

B5

B4

B3

B2 B1 B0

res

res res res res

A1

A0

Register 3 is used to control input data format and polarity,

attenuation channel control, system clock frequency, sam-

pling frequency and infinite zero detection.

format. A “LOW” on bit 0 sets the format to “Normal”

(MSB-first, right-justified Japanese format) and a “HIGH”

(LRP) is used to select the polarity of LRCIN (sample rate

clock). When bit 1 is “LOW”, left channel data is assumed

when LRCIN is in a “HIGH” phase and right channel data

is assumed when LRCIN is in a “LOW” phase. When bit

1 is “HIGH”, the polarity assumption is reversed.

Bit 2 (ATC) is used for controlling the attenuator. When

bit 2 is “HIGH”, the attenuation data loaded in program

Register 0 is used for both left and right channels. When

bit 2 is “LOW”, the attenuation data for each register is

applied separately to left and right channels.

Bit 3 (SYS) is the system clock selection. When bit 3 is

“LOW”, the system clock frequency is set to 384f

Bits 4 (DSR0) and 5 (DSR1) are used to control multiples

of the sampling rate:

DSR1

DSR0

Multiple

0

0

Normal

32/44.1/48kHz

0

1

Double

64/88.2/96kHz

1

0

One-half

16/22.05/24kHz

1

1

Reserved

Not Defined