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PCM1721 Datasheet(PDF) 15 Page - Burr-Brown (TI) |
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PCM1721 Datasheet(HTML) 15 Page - Burr-Brown (TI) |
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15 / 16 page ![]() ® 15 PCM1721 FIGURE 15. 5-Level ∆Σ Modulator Block Diagram. Out 48f S (384fS) 64f S (256fS) In 8f S 18-Bit + + + 4 3 2 1 0 5-level Quantizer + – + Z–1 + – + Z–1 + + Z–1 THEORY OF OPERATION The delta-sigma section of PCM1721 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level delta- sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 15. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modu- lator and the internal 8X interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 16. FIGURE 16. Quantization Noise Spectrum. 3rd ORDER ∆Σ MODULATOR Frequency (kHz) 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 5 10 15 20 25 |
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