PCM1721 datasheet(14/16 Pages) BURR-BROWN

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PCM1721

DGND

AGND

Digital

Power Supply

Analog

Power Supply

1024 system (XTI) clocks

Reset

Reset Removal

XTI Clock

Internal Reset

RSTB

50% of V

RST

(1)

NOTE: (1) t

RST = 20ns min

1024 system (= XTI) clocks

Reset

Reset Removal

2.6V

2.2V

1.8V

CC/VDD

Internal Reset

XTI Clock

FIGURE 12. Internal Power-On Reset Timing.

FIGURE 13. RSTB-Pin Reset Timing.

Reset

PCM1721 has both internal power-on reset circuit and the

RSTB pin (pin 9) which accepts an external forced reset by

RSTB = LOW. For internal power on reset, initialize (reset)

is done automatically at power on VDD >2.2V (typ). During

internal reset = LOW, the output of the DAC is invalid and

the analog outputs are forced to VCC/2. Figure 12 illustrates

the timing of internal power on reset.

PCM1721 accepts an external forced reset when RSTB = L.

During RSTB = L, the output of the DAC is invalid and the

analog outputs are forced to V

CC/2 after internal initialize

(1024 system clocks count after RSTB = H.) Figure 13

illustrates the timing of RSTB pin reset.

POWER SUPPLY

CONNECTIONS

PCM1721 has three power supply connections: digital (VDD),

analog (V

CC), and PLL (VCP). Each connection also has a

separate ground return pin. It is acceptable to use a common

+5V power supply for all three power pins. If separate

supplies are used without a common connection, the delta

between the supplies during ramp-up time must be less than

0.6V. An application circuit to avoid a power-on latch-up

condition is shown in Figure 14.

BYPASSING POWER SUPPLIES

The power supplies should be bypassed as close as possible

to the unit. Refer to Figure 17 for optimal values of bypass

capacitors. Its is also recommended to include a 0.1

µF ce-

ramic capacitor in parallel with the 10

µF tantalum capacitor.

FIGURE 14. Latch-up Prevention Circuit.

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