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AM1806 Datasheet(PDF) 55 Page - Texas Instruments |
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AM1806 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 245 page  AM1806 www.ti.com SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014 4 Device Configuration 4.1 Boot Modes This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does not support dedicated hardware boot modes. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins. See Using the OMAP-L1x8 Bootloader Application Report (SPRAB41) for more details on the ROM Boot Loader. The following boot modes are supported: • NAND Flash boot – 8-bit NAND – 16-bit NAND (supported on ROM revisions after d800k002 -- see the bootloader documents mentioned above to determine the ROM revision) • NOR Flash boot – NOR Direct boot (8-bit or 16-bit) – NOR Legacy boot (8-bit or 16-bit) – NOR AIS boot (8-bit or 16-bit) • HPI Boot • I2C0/I2C1 Boot – EEPROM (Master Mode) – External Host (Slave Mode) • SPI0/SPI1 Boot – Serial Flash (Master Mode) – SERIAL EEPROM (Master Mode) – External Host (Slave Mode) • UART0/UART1/UART2 Boot – External Host • MMC/SD0 Boot 4.2 SYSCFG Module The following system level features of the chip are controlled by the SYSCFG peripheral: • Readable Device, Die, and Chip Revision ID • Control of Pin Multiplexing • Priority of bus accesses different bus masters in the system • Capture at power on reset the chip BOOT pin values and make them available to software • Control of the DeepSleep power management function • Enable and selection of the programmable pin pullups and pulldowns • Special case settings for peripherals: – Locking of PLL controller settings – Default burst sizes for EDMA3 transfer controllers – Selection of the source for the eCAP module input capture (including on chip sources) – McASP AMUTEIN selection and clearing of AMUTE status for the McASP – Control of the reference clock source and other side-band signals for both of the integrated USB PHYs – Clock source selection for EMIFA – DDR2 Controller PHY settings Copyright © 2010–2014, Texas Instruments Incorporated Device Configuration 55 Submit Documentation Feedback Product Folder Links: AM1806 |
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