DAC7614EB datasheet(10/17 Pages) TI1

10 / 17 page

DAC7614

REFERENCE INPUTS

The reference inputs, VREFL and VREFH, can be any voltage

between VSS + 2.25V and VDD – 2.25V provided that

VREFH is at least 1.25V greater than VREFL. The minimum

output of each DAC is equal to VREFL – 1LSB plus a small

offset voltage (essentially, the offset of the output op amp).

The maximum output is equal to VREFH plus a similar

offset voltage. Note that VSS (the negative power supply)

must either be connected to ground or must be in the range

of –4.75V to –5.25V. The voltage on VSS sets several bias

points within the converter. If VSS is not in one of these two

configurations, the bias values may be in error and proper

operation of the device is not guaranteed.

The current into the reference inputs depends on the DAC

output voltages and can vary from a few microamps to

approximately 0.6 milliamp. Bypassing the reference volt-

age or voltages with a 0.1

µF capacitor placed as close as

possible to the DAC7614 package is strongly recommended.

DIGITAL INTERFACE

Figure 3 and Table I provide the basic timing for the

DAC7614. The interface consists of a serial clock (CLK),

serial data (SDI), and a load DAC signal (LOADDACS). In

addition, a chip select (CS) input is available to enable serial

communication when there are multiple serial devices. An

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tDS

Data Valid to CLK Rising

tDH

Data Held Valid after CLK Rises

tCH

CLK HIGH

tCL

CLK LOW

tCSS

CS LOW to CLK Rising

tCSH

CLK HIGH to CS Rising

tLD1

LOADDACS HIGH to CLK Rising

tLD2

CLK Rising to LOADDACS LOW

tLDDW

LOADDACS LOW Time

tRSSH

RESETSEL Valid to RESET LOW

tRSTW

RESET LOW Time

Settling Time

µs

FIGURE 3. DAC7614 Timing.

TABLE I. Timing Specifications (TA = –40°C to +85°C).

asynchronous reset input (RESET) is provided to simplify

start-up conditions, periodic resets, or emergency resets to a

known state.

The DAC code and address are provided via a 16-bit serial

interface as shown in Figure 3. The first two bits select the

DAC register that will be updated when LOADDACS goes

LOW (see Table II). The next two bits are not used. The last

12 bits is the DAC code which is provided, most significant

bit first.

(MSB)

(LSB)

SDI

CLK

LOADDAC

D11

D10

SDI

CLK

LOADDAC

RESET

OUT

tcss

LD1

LD2

LDDW

RSTW

RSSH

CSH

1 LSB

ERROR BAND

1 LSB

ERROR BAND

RESETSEL

DAC7614EB Datasheet(PDF) 10 Page - Texas Instruments

DAC7614EB Datasheet(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL