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DP83850C Datasheet(PDF) 28 Page - National Semiconductor (TI) |
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DP83850C Datasheet(HTML) 28 Page - National Semiconductor (TI) |
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28 / 37 page ![]() 28 www.national.com 6.0 A.C. and D.C. Specifications (Continued) 6.2 A.C. Specifications 6.2.1 Receive Timing Note 1: “CRSx” and “RXEx” refer to any of the CRS[11:0] signals. In the event of a collision (more than one CRS is active) none of the RXE signals will be asserted. Note 2: If, after 4 RXC clocks from CRSx going high, no aligned data is received, the DP83850C 100RIC will repeat the JAM pattern. Description Min Max Units T0 CRSx to RXEx assertion delay (Note 1) 18 ns T1 CRSx to RXEx de-assertion delay with no collision 3 5 LCK T2 CRSx to RX_DV delay requirement (Note 2) 40 ns Description Min Max Units T3 /IRD_V setup to IRD_CK high 2 ns T4 /IRD_V hold from IRD_CK high 2 ns T5 IRD[3:0] or /IRD_ER setup to IRD_CK high 2 ns T6 IRD[3:0] or /IRD_ER hold from IRD_CK high 2 ns |
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