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DP83850C Datasheet(PDF) 33 Page - National Semiconductor (TI) |
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DP83850C Datasheet(HTML) 33 Page - National Semiconductor (TI) |
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33 / 37 page ![]() 33 www.national.com 6.0 A.C. and D.C. Specifications (Continued) 6.2.7 Serial Register Write Timing Note 12:Although the high or low time may be as small as 40ns, the RDC cycle time is limited to 2.5 MHz. Note 13:Serial data will be gated from RDIO to GRDIO during write operation when the “phy_access” bit in the CONFIG register is set. Description Min Max Units T28 RDC period 400 ns T29 RDC high time12 40 ns T30 RDC low time12 40 ns T31 RDC to BRDC delay 25 ns T32 RDIO setup to RDC high 10 ns T33 RDIO hold from RDC high 10 ns T34 RDIO to GRDIO delay13 25 ns T35 /SDV setup to RDC high 10 ns T36 /SDV hold from RDC high 10 ns |
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