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DP83850C Datasheet(PDF) 17 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83850C
Description  100 Mb/s TX/T4 Repeater Interface Controller (100RIC??
PDF  37 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83850C Datasheet(HTML) 17 Page - National Semiconductor (TI)

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4.0 Registers (Continued)
4.2 Page 1 Register Map
4.3 Configuration Register (CONFIG)
Address
(hex)
Name
Access
Description
0
CONFIG
r/w
Sets the DP83850C configuration (same as page 0 CONFIG register).
1
PAGE
r/w
Select either register page 0 or 1.
2
-
-
Reserved
3
-
-
Reserved
4
SIREV
read only Silicon revision code.
5 - 7
-
-
Reserved
8 - B
P6_SE ...
P6_PART
r/w
Port 6 management counters (as per ports 0, 1 above).
C - F
P7_SE ...
P7_PART
r/w
Port 7 management counters (as per ports 0, 1 above).
10 - 13
P8_SE ...
P8_PART
r/w
Port 8 management counters (as per ports 0, 1 above).
14 - 17
P9_SE ...
P9_PART
r/w
Port 9 management counters (as per ports 0, 1 above).
18 - 1B
P10_SE ...
P10_PART
r/w
Port 10 management counters (as per ports 0, 1 above).
1C - 1F
P11_SE ...
P11_PART
r/w
Port 11 management counters (as per ports 0,1 above).
Page 0
Address 0h
Page 1
Address 0h
Bit
Bit Name
Access
Bit Description
D15 - D6
reserved
-
For compatibility with future enhanced versions these bits must be written as zero.
They are undefined when read.
D5
REGEN_PRE
r/w
Regenerate Preamble: This bit may be used to overwrite/change the repeater mode
(TX or T4) that is set by the MODE[1:0] pins at power-up. If MODE[1:0] is 1, 1 then
this bit is set, otherwise this bit will be zero.
The time when the preamble is regenerated depends upon the type of the PHY (ei-
ther TX or T4 PHYs) attached to the repeater. For a TX PHY, preamble is regenerat-
ed approximately 4 clocks (RXC) after the /IR_ACTIVE assertion, and for a T4 PHY,
preamble is regenerated approximately 12 clocks after the /IR_ACTIVE assertion.
D4
MGTEN
r/w
Management Enable: This bit enables all the management counters.
0:
Management Counters disabled (default).
1:
Management Counters enabled.
Note: The management counters can only be reliably written to when they are dis-
abled.
D3
COL_LIMIT32
r/w
This bit configures the collision limit for Auto-Partitioning algorithm:
0:
Consecutive Collision Limit set to 64 consecutive collisions (default). A port will
be partitioned on the 65th consecutive collision.
1:
Consecutive Collision Limit set to 32 consecutive collisions. A port will be parti-
tioned on the 33rd consecutive collision.
D2
DIS_PART
r/w
This bit disables the Auto-Partitioning algorithm:
0:
Auto-Partitioning is not disabled (default).
1:
Auto-Partitioning is disabled.



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