REV. A

AD7475/AD7495

–13–

in the desired mode of operation, and thus a dummy cycle is not

required to change mode, then neither is a dummy cycle required

to place the track-and-hold into track. If no current monitoring

facility is available, the relevant dummy cycle(s) should be per-

formed to ensure the part is in the required mode.

POWER VERSUS THROUGHPUT RATE

By using the partial power-down mode on the AD7475/AD7495

when not converting, the average power consumption of the

ADC decreases at lower throughput rates. Figure 18 shows

how, as the throughput rate is reduced, the part remains in its

partial power-down state longer and the average power consump-

tion over time drops accordingly.

THROUGHPUT – kSPS

100

0.001

0

50

100

0.01

0.1

1

10

150

200

250

300

350

AD7495 5V

SCLK = 20MHz

AD7495 3V

SCLK = 20MHz

AD7475 5V

SCLK = 20MHz

AD7475 3V

SCLK = 20MHz

Figure 18. AD7495 Power vs. Throughput for Partial

Power-Down

For example if the AD7495 is operated in a continuous sampling

mode with a throughput rate of 100 kSPS and an SCLK of

down mode between conversions, then the power consumption

is calculated as follows. The maximum power dissipation during

from partial power-down is one dummy cycle, i.e., 1

µs, and the

remaining conversion time is another cycle, i.e., 1

µs, then the

AD7495 can be said to dissipate 13 mW for 2

µs during each

conversion cycle. For the remainder of the conversion cycle,

8

µs, the part remains in partial power-down mode. The AD7495

can be said to dissipate 1.15 mW for the remaining 8

µs of the

conversion cycle. If the throughput rate is 100 kSPS, the cycle

time is 10

µs and the average power dissipated during each cycle

is (2/10)

(13 mW) + (8/10)

= 3 V, SCLK = 20 MHz and the device is again in partial power-

down mode between conversions, the power dissipated during

normal operation is 6 mW. The AD7495 can be said to dissipate

6 mW for 2

µs during each conversion cycle and 0.69 mW for the

remaining 8

µs where the part is in partial power-down. With a

throughput rate of 100 kSPS, the average power dissipated during

each conversion cycle is (2/10)

(6 mW) + (8/10)

(0.69 mW)

= 1.752 mW. Figure 18 shows the power versus throughput rate

when using the partial power-down mode between conversions

with both 5 V and 3 V supplies for both the AD7475 and AD7495.

For the AD7475, partial power-down current is lower than that

of the AD7495.

Full power-down mode is intended for use in applications with

slower throughput rates than required for the partial power-

down mode. It is necessary to leave 650

µs for the AD7495 to

be fully powered up from full power-down before initiating a

conversion. Current consumptions between conversions is typi-

cally less than 1

µA.

Figure 19 shows a typical graph of current versus throughput for

the AD7495 while operating in different modes. At slower

throughput rates, e.g., 10 SPS to 1 kSPS, the AD7495 was

operated in Full Power-Down mode. As the throughput rate

increased, up to 100 kSPS, the AD7495 was operated in Partial

Power-Down mode, with the part being powered down between

conversions. With throughput rates from 100 kSPS to 1 MSPS,

the part operated in Normal mode, remaining fully powered up

at all times.

THROUGHPUT – SPS

2.0

10

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

100

1k

10k

100k

1M

FULL

POWER-DOWN

PARTIAL

POWER-DOWN

NORMAL

Figure 19. Typical AD7495 Current vs. Throughput

SERIAL INTERFACE

Figure 20 shows the detailed timing diagram for serial interfacing

to the AD7475/AD7495. The serial clock provides the conversion

clock and also controls the transfer of information from the

AD7475/AD7495 during conversion.

CS initiates the data transfer and conversion process. The falling

edge of

CS puts the track and hold into hold mode, takes the bus

out of three-state, and the analog input is sampled at this point.

SCLK

1

5

13

15

SDATA

FOUR LEADING ZEROS

THREE-STATE

2

34

16

THREE-STATE

DB11

DB10

DB2

DB0

14

0

0

0

0

B

DB1

CS

Figure 20. Serial Interface Timing Diagram