10%

30Ps min

CLC020

www.ti.com

SNLS046E – FEBRUARY 2000 – REVISED APRIL 2013

LOCK DETECT

The Lock Detect output of the phase-frequency detector indicates the PLL lock condition. It is a logic HIGH

when the loop is locked. The output is CMOS/TTL-compatible and is suitable for driving other CMOS devices or

a LED indicator.

SERIAL DATA OUTPUT BUFFER

The current-mode serial data outputs provide low-skew complimentary or differential signals. The output buffer

design can drive 75

Ω coaxial cables (AC-coupled) or 10k/100k ECL/PECL-compatible devices (DC-coupled).

±10% when DC-coupled into 75

Ω (See APPLICATION INFORMATION for details). The 75Ω resistors connected

to the SDO outputs are back-matching resistors. No series back-matching resistors should be used. SDO output

21 and 24, are provided for the serial output driver.

POWER-ON RESET

The CLC020 has an internally controlled, automatic, power-on reset circuit. This circuit clears TRS detection

circuitry, all latches, registers, counters and polynomial generators and disables the serial output. The SDO

outputs are tri-stated during power-on reset. The part will remain in the reset condition until the parallel input

clock is applied.

Figure 5. Power-On Reset Sequence

BUILT-IN SELF-TEST (BIST)

The CLC020 has a built-in self-test (BIST) function. The BIST performs a comprehensive go-no-go test of the

device. The test uses either a full-field color bar for NTSC or a PLL pathological for PAL as the test data pattern.

Data is input internally to the input data register, processed through the device and tested for errors. Table 1

gives device pin functions and Table 2 gives the test pattern codes used for this function. The signal level at

Test_Output, pin 26, indicates a pass or fail condition.

The BIST is initiated by applying the code for the desired BIST to D0 throught D3 (D9 through D4 are 00h) and a

those inputs D0 through D3 which require a logic-1 need be pulled high. After the Lock_Detect output goes high

(true) indicating the VCO is locked on frequency, TPG_Enable, pin 17, is then taken to a logic high. TPG_Enable

may be temporarily connected to the Lock_Detect output to automate BIST operation. Test_Output, pin 26, is

monitored for a pass/fail indication. If no errors have been detected, this output will go to a logic high level

approximately 2 field intervals after TPG_Enable is taken high. If errors have been detected in the internal

circuitry of the CLC020, Test_Output will remain low until the test is terminated. The BIST is terminated by taking

TPG_Enable to a logic low. Continuous serial data output is available during the test.

Copyright © 2000–2013, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: CLC020