CLC020

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SNLS046E – FEBRUARY 2000 – REVISED APRIL 2013

The jitter test setup used to obtain values quoted in the data sheet consists of:

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Texas Instruments SD020EVK, CLC020 evaluation kit

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Tektronix TG2000 signal generation platform with DVG1 option

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Tektronix VM700T Option 1S Video Measurement Set

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Tektronix TDS 794D, Option C2 oscilloscope

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Tektronix P6339A passive probe

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75 Ohm coaxial cable, 3ft., Belden 8281 or RG59 (2 required)

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ECL-to-TTL/CMOS level converter/amplifier, Figure 11

Apply the black-burst reference clock from the TG2000 signal generator's BG1 module 27MHz clock output to the

level converter input. The clock amplitude converter schematic is shown in Figure 10. Adjust the input bias

control to give a 50% duty cycle output as measured on the oscilloscope/probe system. Connect the level

SD020EVK to operate in the NTSC colour bars, BIST mode. Configure the VM700T to make the jitter

measurement in the jitter FFT mode at the frame rate with 1kHz filter bandwidth and Hanning window. Configure

the setup as shown in Figure 10. Switch the test equipment on (from standby mode) and allow all equipment

temperatures stabilize per manufacturer's recommendation. Measure the jitter value after allowing the

instrument's reading to stabilize (about 1 minute). Consult the VM700T Video Measurement Set Option 1S Serial

Digital Measurements User Manual (document number 071-0074-00) for details of equipment operation.

The VM700T measurement system's jitter floor specification at 270Mbps is given as 200ps ±20% (100ps ±5%

typical) of actual components from 50Hz to 1MHz and 200ps +60%, -30% of actual components from 1MHz to

10MHz. To obtain the actual residual jitter of the CLC020, a root-sum-square adjustment of the jitter reading

must be made to compensate for the measurement system's jitter floor specification. For example, if the jitter

the reading as given above apply.

Figure 10. Jitter Test Circuit

Figure 11. ECL-to-TTL/CMOS level converter/amplifer

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