COP8CCE9IMT7SLASHNOPB datasheet(21/101 Pages) TI1

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COP8CCE9

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SNOS978J – JUNE 2001 – REVISED MARCH 2013

For the purpose of erasing and rewriting the Flash Memory, it is organized in pages of 64 bytes as show in

Table 3.

Table 3. Available Memory Address Ranges

Flash Memory

Program Memory

Option Register

Data Memory

Segments

Maximum RAM

Device

Page Size

Size (Flash)

Address (Hex)

Size (RAM)

Available

Address (HEX)

(Bytes)

COP8CBE9

8192

1FFF

256

0-1

017F

COP8CCE9

DATA MEMORY

The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration,

Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and

counters associated with the timers and the USART (with the exception of the IDLE timer). Data memory is

addressed directly by the instruction or indirectly by the B, X and SP pointers.

The data memory consists of 256 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at addresses

0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ

(decrement register and skip if zero) instruction. The memory pointer registers X, SP, B and S are memory

mapped into this space at address locations 0FC to 0FF Hex respectively, with the other registers being available

for general usage.

The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC)

are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested.

The accumulator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

DATA MEMORY SEGMENT RAM EXTENSION

Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).

The data store memory is either addressed directly by a single byte address within the instruction, or indirectly

relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte

address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address

divides the data store memory into two separate sections as outlined previously. With the exception of the RAM

the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine

whether or not the base address range (from 0000 – 00FF) is extended. If this upper bit equals one (representing

address range 0080 – 00FF), then address extension does not take place. Alternatively, if this upper bit equals

zero, then the data segment extension register S is used to extend the base address range from 0000 – 007F to

XX00 – XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions

are located from addresses 0100 – 017F for data segment 1, 0200 – 027F for data segment 2, etc., up to FF00 –

FF7F for data segment 255. The base address range from 0000 – 007F represents data segment 0.

Refer to Table 3, to determine available RAM segments for this device.

Figure 9illustrates how the S register data memory extension is used in extending the lower half of the base

address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32

kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an

additional upper base segment of 128 bytes. Furthermore, all addressing modes are available for all data

segments. The S register must be changed under program control to move from one data segment (128 bytes)

to another. However, the upper base segment (containing the 16 memory registers, I/O registers, control

registers, etc.) is always available regardless of the contents of the S register, since the upper base segment

(address range 0080 to 00FF) is independent of data segment extension.

The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment

(Segment 0), regardless of the contents of the S register. The S register is not changed by these instructions.

Consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. The

stack pointer will be initialized to point at data memory location 006F as a result of reset.

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